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rev. 4202b?scr?07/03 1 features 80c51 core : ? 6 clocks per instruction ? speed up to 16 mhz 768 bytes ram at83c5122: 32 kbytes rom at83c5123: 30 kbytes rom at85c5122: 32 kbytes code ram and 32 kbytes rom AT89C5122 : 32 kbytes flash at85ec5122, at83ec5123, at83ec5122: additional 512 bytes eeprom (at24c04) multi-protocol smart card interface ? certified according to iso7816, emv2000, gie-cb and whqm standards ? asynchronous protocols t = 0 and t = 1, with direct and inverse modes ? step-up/down converter with programmable voltage output: 5v and 3v (60 ma), 1.8v (20 ma) ? 4 kv esd protection (mil/std 833 class 3) alternate card support with clk, io and rst usb module with 7 endpoints programmable with in or out directions and with iso, bulk or interrupt transfers uart with integrated baud rate generator (brg) 8 mhz on-chip oscillator analog pll for 96 mhz synthesis, possible 48 mhz clock input two 16-bit timer/counters: t0 and t1 hardware watchdog and power-fail detector (pfd) idle and power-down modes self powered usb low power ? 30 ma maximum operating current (at 32 mhz x1) ? 100 a maximum power-down current at 5.4v (without smart card and usb) voltage range: 3.6 to 5.5v for at8xc5122 version: ? keyboard interrupt interface on port 5 (8 bits) ? five 8-bit i/o ports, one 6-bit ? spi interface (master slave) ? packages: vqfp64, plcc28 ? seven led outputs with programmable current sources: 2-4-10 ma for at8xc5123 version: ? four led outputs with programmable current sources: 2-4-10 ma ? two 8-bit i/o ports, one 6-bit i/o port, one i/o bit (on lqp32 package) ? packages: lqfp32, plcc28 c51 microcontroller with usb and smart card reader interfaces at83c5122 at83ec5122 at85c5122 at85ec5122 AT89C5122 at83c5123 at83ec5123 preliminary
2 at8xc5122/23 4202b ? scr ? 07/03 description at8xc5122 is a high-performance cmos derivative of the 80c51 8-bit microcontrollers optimized for usb keyboard with smart card reader applications. at8xc5122 retains the features of the atmel 80c51 with 32 kbytes rom capacity, 768 bytes of internal ram, a 4-level interrupt system, two 16-bit timer/counters (t0/t1), a full duplex enhanced uart (euart) with baud rate generator (brg) and an on-chip oscillator. in addition, at8xc5122 has a usb 2.0 full-speed function controller with seven end- points, a multi-protocol smart card interface, a dual data pointer, seven programmable led current sources (2-4-10 ma) and a hardware watchdog. at8xc5122 flash ram version and at8xc5122 code ram version with 32 kbytes memory can be loaded by in-system programming (isp) software residing in the on- chip rom from usb or uart. at8xc5122 have 2 software-selectable modes of reduced activity for further reduction in power consumption. at8xc5123 is a low pin count of the at8xc5122. this version doesn ? t have the key- board and the spi interfaces. the plcc28 packages for at8xc5122 and at8xc5123 have the same pinout. the at8xc5123 is also proposed in a vqfp32 package. at8xc5122 and at8xc5123 are proposed with a 512 bytes eeprom (at24c04) and respectively named at8xec5122 and at8xec5123.
3 at8xc5122/23 4202b ? scr ? 07/03 at8xc5122 block diagram at8xc5123 block diagram timer 0 int ram 256 x 8 t0 t1 rxd txd xtal2 xtal1 euart cpu timer 1 int1 ctrl int0 c51 core p1 ib-bus rom* xtal osc xram 512 x 8 scib cc8 crst cpres cio cc4 cclk cvcc 8 li external memory 32k x8 sck led led0-6 out pll (1) watchdog cvss p2 p0 ea psen ale dc/dc converter level shifters por pfd usb d+ d- i/os p3 8 i/os p4 6 i/os p5 8 i/os and ports kb cio1 cclk1 crst1 p5 alternate card spi v ref miso mosi ss pllf avcc avss vss vcc brg rst parallel i/o ports dvcc cram* 32k x8 flash* 32k x8 * see versions timer 0 int ram 256 x 8 t0 t1 rxd txd xtal2 xtal1 euart cpu timer 1 int1 ctrl int0 c51 core p1 ib-bus rom xtal osc xram 512 x 8 scib cc8 crst cpres cio cc4 cclk cvcc 8 li 30k x8 led led0-3 out pll watchdog cvss dc/dc converter level shifters por pfd usb d+ d- i/os p3 8 i/os p4 2 i/os p5 cio1 cclk1 crst1 alternate card v ref pllf avcc avss vss vcc brg rst parallel i/o ports dvcc 1 i/os
4 at8xc5122/23 4202b ? scr ? 07/03 pin description figure 1. vqfp64 pinout (only for at8xc5122) figure 2. plcc28 pinout 62 61 60 59 58 63 57 56 55 54 53 p0.1/ad1 p0.3/ad3 p0.5/ad5 p0.7/ad7 d+ p4.1/mosi p4.0/miso p4.2/sck p4.5/led6 p3.1/txd p4.3/led4 p4.4/led5 p3.6/wr/led2 d- rst xtal1 xtat2 p2.5/a13 p2.4/a12 p2.2/a10 p2.1/a9 p2.0/a8 p1.5/crst p1.4/cclk li p2.3/a11 2 3 4 5 6 7 8 9 10 11 48 47 46 45 44 43 42 41 40 39 38 vqfp64 64 52 12 13 36 37 vcc vss p5.0/kb0 ea p3.7/rd/led3 51 50 avss 49 avcc p3.3/int1 35 33 34 p3.4/t0/led1 p3.5/t1/crst1 cvcc 14 15 16 cvss 31 32 p0.0/ad0 p1.2/cpres p0.2/ad2 p0.4/ad4 p0.6/ad6 p1.6/ss p2.7/a15 p2.6/a14 p1.7/cclk1 p5.1/kb1 p5.2/kb2 p5.3/kb3 p5.4/kb4 p5.5/kb5 p5.6/kb6 p5.7/kb7 p3.2/int0/led0/cio1 v ref p1.3/cc4 pllf ale psen dvcc p1.1/cc8 p1.0/cio p3.0/rxd 1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 p1.0/cio plcc28 p3.1/txd p1.4/cclk vss p1.3/cc4 dvcc p1.1/cc8 xtal1 xtat2 li vcc p3.7/led3 cvcc cvss p3.6/led2 rst p1.5/crst p3.3/int1 p1.2/cpres d- d+ avcc avss v ref pllf p3.2/int0/led0 p3.4/t0/led1 p3.0/rxd 1 2 3 4282726 5 6 7 8 9 10 11 25 24 23 22 21 20 19 15 14 13 12 1617 18
5 at8xc5122/23 4202b ? scr ? 07/03 figure 3. lqfp32 pinout (only for at83c5123) figure 4. plcc68 pinout (engineering package only for at85c5122, check availability with atmel sales office) p1.0/cio lqfp32 p3.1/txd p1.4/cclk p5.0 p1.3/cc4 dvcc p1.1/cc8 xtal1 xtat2 li vcc p3.7/led3 cvcc cvss p3.6/led2 p1.5/crst p3.3/int1 p1.2/cpres d- d+ avcc avss pllf p3.2/int0 /led0/cio1 p3.4/led1/t0 p3.0/rxd 28 27 26 1 2 3 4 5 6 7 24 23 22 21 20 19 18 12 11 10 9131415 vss 8 16 rst 17 p1.6 p3.5/t1/crst1 p1.7/cclk1 vref 25 29 30 31 32 62 61 60 59 58 63 57 56 55 54 53 p0.1/ad1 p0.3/ad3 p0.5/ad5 p0.7/ad7 d+ p4.1/mosi p4.0/miso p4.2/sck p4.5 p1.1/cc8 p4.3 p4.4 p3.6/wr d- rst xtal2 xtat1 p2.5/a13 p2.4/a12 p2.2/a10 p2.1/a9 p2.0/a8 p3.1/txd p1.4/cclk li p2.3/a11 1 2 3 4 5 6 7 8 9 10 11 48 47 46 45 44 43 42 41 40 39 38 plcc68 64 52 12 13 36 37 vcc vss p5.0 ea p3.7/rd 51 50 avss 49 avcc p3.3/int1 35 33 34 p3.4/t0 p3.5/t1/crst1 cvcc 14 cvss p1.0/cio 32 p0.0/ad0 p3.0/rxd p0.2/ad2 p0.4/ad4 p0.6/ad6 p1.6/ss p2.7/a15 p2.6/a14 p1.7/cclk1 p5.1 p5.2 p5.3 p5.4 p5.5 p5.6 p5.7 p3.2/int0/cio1 vref p1.3/cc4 pllf ale psen dvcc p1.2/cpres p1.5/crst n/a n/a 1 68 67 66 65 64 63 62 61 2 3 4 5 6 7 8 9 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 10 11 12 13 14 15 16 17 18 19 20 21 22 24 25 26 62 61 60 59 58 63 57 56 55 54 53 64 52 51 50 49 35 36 37 38 39 40 41 42 43 34 33 32 31 30 29 28 27 23 nc nc
6 at8xc5122/23 4202b ? scr ? 07/03 signals all the signals are detailed in table 1: table 1. pinout description port vqfp64 lqfp32 plcc68 plcc28 internal power supply esd i/o reset level alt reset config conf 1 conf 2 conf 3 led p0.0 30 - 41 - vcc 2kv i/o float ad0 p0 kb_out push-pull p0.1 29 - 40 - vcc 2kv i/o float ad1 p0 kb_out push-pull p0.2 28 - 39 - vcc 2kv i/o float ad2 p0 kb_out push-pull p0.3 27 - 38 - vcc 2kv i/o float ad3 p0 kb_out push-pull p0.4 25 - 36 - vcc 2kv i/o float ad4 p0 kb_out push-pull p0.5 24 - 35 - vcc 2kv i/o float ad5 p0 kb_out push-pull p0.6 23 - 34 - vcc 2kv i/o float ad6 p0 kb_out push-pull p0.7 22 - 33 - vcc 2kv i/o float ad7 p0 kb_out push-pull p1.0 64 32 9 4 cvcc 4kv i/o 0 cio port51 cvcc inactive at reset p1.1 3 3 12 7 cvcc 4kv i/o 0 cc8 port51 cvcc inactive at reset p1.2 2 2 11 6 vcc 2kv i/o 1 cpres port51 weak & medium pull-up can be disconnected p1.3 9 5 18 9 cvcc 4kv i/o 0 cc4 port51 cvcc inactive at reset p1.4 12 6 21 10 cvcc 4kv o 0 cclk push-pull cvcc inactive at reset p1.5 6 4 15 8 cvcc 4kv o 0 crst push-pull cvcc inactive at reset p1.6 47 23 58 - vcc 2kv i/o 1 ss port51 p1.7 62 31 7 - vcc 2kv i/o 1 cclk1 port51 p2.0 58 - 3 - vcc 2kv i/o 1 a8 port51 push-pull kb_out input wpu p2.1 57 - 2 - vcc 2kv i/o 1 a9 port51 push-pull kb_out input wpu p2.2 56 - 1 - vcc 2kv i/o 1 a10 port51 push-pull kb_out input wpu p2.3 52 - 65 - vcc 2kv i/o 1 a11 port51 push-pull kb_out input wpu p2.4 51 - 64 - vcc 2kv i/o 1 a12 port51 push-pull kb_out input wpu p2.5 50 - 63 - vcc 2kv i/o 1 a13 port51 push-pull kb_out input wpu p2.6 49 - 62 - vcc 2kv i/o 1 a14 port51 push-pull kb_out input wpu p2.7 46 - 57 - vcc 2kv i/o 1 a15 port51 push-pull kb_out input wpu
7 at8xc5122/23 4202b ? scr ? 07/03 p3.0 45 22 56 24 vcc 2kv i/o 1 rxd port51 push-pull kb_out input wpu p3.1 48 24 59 25 vcc 2kv i/o 1 txd port51 push-pull kb_out input wpu p3.2 43 20 54 23 vcc 2kv i/o 1 int0 port51 led0 p3.3 41 19 52 22 vcc 2kv i/o 1 int1 port51 push-pull kb_out input wpu p3.4 39 18 50 21 vcc 2kv i/o 1 t0 port51 push-pull kb_out input wpu led1 p3.5 44 21 55 - vcc 2kv i/o 1 t1 port51 p3.6 36 17 47 20 vcc 2kv i/o 1 wr port51 led2 p3.7 26 13 37 16 vcc 2kv i/o 1 rd port51 led3 p4.0 42 - 53 - vcc 2kv i/o 1 miso port51 p4.1 40 - 51 - vcc 2kv i/o 1 mosi port51 p4.2 38 - 49 - vcc 2kv i/o 1 sck port51 p4.3 37 - 48 - vcc 2kv i/o 1 port51 push-pull kb_out input mpu led4 p4.4 35 - 46 - vcc 2kv i/o 1 port51 push-pull kb_out input mpu led5 p4.5 33 - 44 - vcc 2kv i/o 1 port51 push-pull kb_out input mpu led6 p4.6 - - 61 - vcc 2kv i/o 1 reserved p4.7 - - 60 - vcc 2kv i/o 1 reserved p5.0 14 7 23 - vcc 2kv i/o 1 kb0 port51 push-pull input mpu input wpu p5.1 13 - 22 - vcc 2kv i/o 1 kb1 port51 push-pull input mpu input wpu p5.2 11 - 20 - vcc 2kv i/o 1 kb2 port51 push-pull input mpu input wpu p5.3 10 - 19 - vcc 2kv i/o 1 kb3 port51 push-pull input wpd input wpu p5.4 8 - 17 - vcc 2kv i/o 1 kb4 port51 push-pull input wpd input wpu p5.5 7 - 16 - vcc 2kv i/o 1 kb5 port51 push-pull input wpd input wpu table 1. pinout description (continued) port vqfp64 lqfp32 plcc68 plcc28 internal power supply esd i/o reset level alt reset config conf 1 conf 2 conf 3 led
8 at8xc5122/23 4202b ? scr ? 07/03 p5.6 5 - 14 - vcc 2kv i/o 1 kb6 port51 push-pull input wpd input wpu p5.7 4 - 13 - vcc 2kv i/o 1 kb7 port51 push-pull input wpd input wpu rst 34 16 45 19 vcc i/0 reset input holding this pin low for 64 oscillator periods while the oscillator is running resets the device. the port pins are driven to their reset conditions when a voltage lower than v il is applied, whether or not the oscillator is running. this pin has an internal pull-up resistor which allows the device to be reset by connecting a capacitor between this pin and vss. asserting rst when the chip is in idle mode or power-down mode returns the chip to normal operation. the output is active for at least 12 oscillator periods when an internal reset occurs. d+ 60 29 5 2 dvcc i/o usb positive data upstream port this pin requires an external 1.5 k ? pull-up to v ref for full speed d- 59 28 4 1 dvcc i/o usb negative data upstream port v ref 61 30 6 3 avcc o usb voltage reference : 3.0 < v ref < 3.6 v v ref can be connected to d+ with a 1.5 k ? resistor. the v ref voltage is controlled by software. xtal 1 31 14 42 17 vcc i input to the on-chip inverting oscillator amplifier to use the internal oscillator, a crystal/resonator circuit is connected to this pin. if an external oscillator is used, its output is connected to this pin. xtal 2 32 15 43 18 vcc o output of the on-chip inverting oscillator amplifier to use the internal oscillator, a crystal/resonator circuit is connected to this pin. if an external oscillator is used, leave xtal2 unconnected. ea 63 - 8 - vcc i external access enable ea must be strapped to ground in order to enable the device to fetch code from external memory locations 0000h to ffffh. if security level 1 is programmed, ea will be latched on reset. ale 21 - 32 - vcc o address latch enable/program pulse: output pulse for latching the low byte of the address during an access to external memory. in normal operation, ale is emitted at a constant rate of 1/6 (1/3 in x2 mode) the oscillator frequency, and can be used for external timing or clocking. note that one ale pulse is skipped during each access to external data memory. this pin is also the program pulse input (prog ) during flash programming. ale can be disabled by setting sfr ? s auxr.0 bit. with this bit set, ale will be inactive during internal fetches psen 15 - 24 - vcc o program strobe enable: the read strobe to external program memory. when executing code from the external program memory, psen is activated twice each machine cycle, except that two psen activations are skipped during each access to external data memory. psen is not activated during fetches from internal program memory. pllf 54 26 67 27 avcc o pll low pass filter input receives the rc network of the pll low pass filter. avcc 55 27 68 28 pwr analog supply voltage avcc is used to supply the on-chip pll and the usb drivers table 1. pinout description (continued) port vqfp64 lqfp32 plcc68 plcc28 internal power supply esd i/o reset level alt reset config conf 1 conf 2 conf 3 led
9 at8xc5122/23 4202b ? scr ? 07/03 vcc 20 12 31 15 pwr supply voltage vcc is used to power the internal voltage regulators and internal i/o ? s li 18 10 29 13 pwr dc/dc input li must be tied to vcc through an external coil and provide the current for the pump charge of the dc/dc converter cvcc 17 9 28 12 pwr card supply voltage cvcc is the programmable voltage output for the card interface. it must be connected to an external decoupling capacitor dvcc 1 1 10 5 pwr digital supply voltage dvcc is used to supply the digital core and internal i/o ? s. it is internally connected to the output of a 3.3v voltage regulator and must be connected to an external decoupling capacitor cvss 19 11 30 14 gnd dc/dc ground cvss is used to sink high shunt currents from the external coil vss 16 8 25 11 gnd digital ground vss is used to supply the buffer ring and the digital core avss 53 25 66 26 gnd analog ground avss is used to supply the on-chip pll and the usb drivers table 1. pinout description (continued) port vqfp64 lqfp32 plcc68 plcc28 internal power supply esd i/o reset level alt reset config conf 1 conf 2 conf 3 led
10 at8xc5122/23 4202b ? scr ? 07/03 i/o port definition ports vs packages table 2. io number vs packages port 0 port 0 has the following functions: ? default function: port 0 is an 8-bit i/o port. ? alternate function: port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. in this application, it uses strong internal pull-ups when emitting 1 ? s and it can drive cmos inputs without external pull-ups. port 0 has the following configurations: ? default configuration: open drain bi-directional i/o port. port 0 pins that have 1 ? s written to them float, and in this state they can be used as high- impedance inputs. ? configuration 2: low speed output, ? kb_out ? ? configuration 3: push-pull output port 1 port 1 has the following functions: ? default function: only port 1.2, p1.6 and p1.7 are standard i/o ? s; the other ports can only be activated with the scib function. ? alternate function and configuration: see table 3. table 3. port 1 description. p0 p1 p2 p3 p4 p5 total vqfp6488888646 lqfp32 8 8 1 17 plcc28 6 6 1 13 plcc6888888848 port alternate function configuration signal description mode description p1.0 cio smart card interface function card i/o port51 cvcc supply: inactive at reset p1.1 cc8 smart card interface function card contact 8 push-pull cvcc supply: zero level at reset p1.2 cpres smart card interface function card presence port51 weak & medium pull-up can be deconnected by software p1.3 cc4 smart card interface function card contact 4 push-pull cvcc supply: zero level at reset p1.4 cclk smart card interface function card clock push-pull cvcc supply: zero level at reset p1.5 crst smart card interface function card reset push-pull cvcc supply: zero level at reset p1.6 ss ss pin of the spi function port51
11 at8xc5122/23 4202b ? scr ? 07/03 note: p1.7 is switched automatically to push-pull when the alternate clock is selected (see table 42 on page 48 ) port 2 port 2 has the following functions: ? default function: port 2 is an 8-bit i/o port. ? alternate function 1: port 2 is also the multiplexed high-order address during accesses to external program and data memory. in this application, it uses strong internal pull-ups when emitting 1 ? s and it can drive cmos inputs without external pull-ups. port 2 has the following configurations: ? default configuration: pseudo bi-directional ? port51 ? digital input/output with internal pull-ups. ? configuration 1: push-pull output ? configuration 2: low speed output, ? kb_out ? configuration 3: input with weak pull-up, ? wpu input ? port 3 port 3 has the following functions: ? default function: port 3 is an 8-bit i/o port. ? alternate functions: see table below port 3 has the following configurations: ? default configuration: pseudo bi-directional ? port51 ? digital input/output with internal pull-ups. ? alternate configurations: see table 4. table 4. port 3 description p1.7 cclk1 alternate smart card clock output port51/p ush-pull port alternate functions configurations signal description mode 1 mode 2 mode 3 mode 4 p3.0 rxd receiver data input (asynchronous) or data input/output (synchronous) of the serial interface push-pull kb_out input wpu p3.1 txd transmitter data output (asynchronous) or clock output (synchronous) of the serial interface push-pull kb_out input wpu p3.2 int0 external interrupt 0 input/timer 0 gate control input led0 p3.3 int1 external interrupt 1input/timer 1 gate control input push-pull kb_out input wpu p3.4 t0 timer 0 counter input push-pull kb_out input wpu led1 p3.5 t1 timer 1 counter input p3.6 wr external data memory write strobe; latches the data byte from port 0 into the external data memory led2 p3.7 rd external data memory read strobe; enables the external data memory. port 3 can drive cmos inputs without external pull-ups led3
12 at8xc5122/23 4202b ? scr ? 07/03 port 4 port 4 has the following functions: ? default function: port 4 is an 6-bit i/o port. ? alternate functions: see table below port 4 has the following configurations: ? default configuration: pseudo bi-directional ? port51 ? digital input/output with internal pull-ups. ? alternate configurations: see table 5.. table 5. port 4 description port 5 port 5 has the following functions: ? default function: port 5 is an 8-bit i/o port. ? alternate function 1: port 5 is an 8-bit keyboard port kb0 to kb7. port 5 has the following configurations: ? default configuration: pseudo bi-directional ? port51 ? digital input/output with internal pull-ups. ? alternate configuration: see table 6.. table 6. port 5 description port alternate functions configurations signal description mode 1 mode 2 mode 3 p4.0 miso spi master in slave out i/o p4.1 mosi spi master out slave in i/o p4.2 sck spi clock p4.3 push-pull kb_out input mpu p4.4 push-pull kb_out input mpu p4.5 push-pull kb_out input mpu port configurations mode 1 mode 2 mode 3 p5.0 push-pull input mpu input wpu first cluster p5.1 push-pull input mpu input wpu p5.2 push-pull input mpu input wpu p5.3 push-pull input wpd input wpu second cluster p5.4 push-pull input wpd input wpu p5.5 push-pull input wpd input wpu p5.6 push-pull input wpd input wpu third cluster p5.7 push-pull input wpd input wpu
13 at8xc5122/23 4202b ? scr ? 07/03 port configuration standard i/o p0 the p0 port is described in figure 5. figure 5. standard input/output p0 quasi-bi-directional output configuration the default port output configuration for standard i/o ports is the quasi-bi-directional output that is common on the 80c51 and most of its derivatives. the ? port51 ? output type can be used as both an input and output without the need to reconfigure the port. this is possible because when the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. when the port outputs a logic low state, it is driven strongly and is able to sink a fairly large current. these features are somewhat similar to an open-drain output except that there are three pull-up transistors in the quasi-bi-directional output that serve different purposes. one of these pull-ups, called the weak pull-up, is turned on whenever the port latch for the pin contains a logic 1. the weak pull-up sources a very small current that will pull the pin high if it is left floating. the weak pull-up can be turned off by the dpu bit in auxr register. a second pull-up, called the medium pull-up, is turned on when the port latch for the pin contains a logic 1 and the pin itself is also at a logic 1 level. this pull-up provides the pri- mary source current for a quasi-bi-directional pin that is outputting a 1. if a pin that has a logic 1 on it is pulled low by an external device, the medium pull-up turns off, and only the weak pull-up remains on. in order to pull the pin low under these conditions, the external device has to sink enough current to overpower the medium pull-up and take the voltage on the port pin below its input threshold. the ? port51 ? is described in figure 6. mux pin addr/data control vcc 1 0 input data port latch data pmos nmos
14 at8xc5122/23 4202b ? scr ? 07/03 figure 6. quasi-bi-directional output push-pull output configuration the push-pull output configuration has the same pull-down structure as both the open drain and the quasi-bi-directional output modes, but provides a continuous strong pull- up when the port latch contains a logic 1. the push-pull mode may be used when more source current is needed from a port output. the push-pull port configuration is shown in figure 7. figure 7. push-pull output input with medium or weak pull-up configuration the input with pull-up (input mpu and input wpu) configuration is shown in figure 8. 2 cpu input pin strong weak medium n p p p clock delay port latch data data dpu (auxr reg.) pmos nmos input pin strong n p port latch data data pmos nmos
15 at8xc5122/23 4202b ? scr ? 07/03 figure 8. input with pull-up input with weak pull-down configuration the input with pull-down (input wpd) configuration is shown in figure 9 figure 9. input with pull-down low speed output configuration the low speed output with low speed t fall and t rise can drive keyboard. the current limitation of the led2ctrl block requires a polarisation current of about 250 a. this block is automatically disabled in power-down mode. the low speed output configuration (kb_out) is shown in figure 10. figure 10. low-speed output input pin data weak p medium p stuck to 0 if medium stuck to 0 if weak input pin data weak n 1 pin p pweakctrl port latch data n n nmos pcon.1 weak led2ctrl input data
16 at8xc5122/23 4202b ? scr ? 07/03 led source current the led configuration is shown in figure 11. figure 11. led source current notes: 1. when switching a low level, ledctrl device has a permanent current of about n ma/15 (n is 2, 4 or 8). 2. the port must be configured to be used as output by means of pmod0 and pmod1 registers and the level of current must be programmed by means of ledcon0 and ledcon1 registers before switching the led on. 3. the value of the pull-up depends on the mode that is selected to configure the port as output. table 7. low speed output configuration input signals outputs signals pin comments pcon.1 port latch data nmos led2ctrl pweakctrl 0001 10 operating mode 0100 01 1010 10 power down mode 1100 01 pin port latch data ledx.0 ledx.1 nmos n n (see note 3) ledctrl input data
17 at8xc5122/23 4202b ? scr ? 07/03 registers reset value = 0000 0x00b table 8. led source current ledx.1 ledx.0 port latch data nmos pin comments 00 0 10 led control disabled 00 1 01 01 0 00 led mode 2 ma 01 1 01 10 0 00 led mode 4 ma 10 1 01 11 0 00 led mode 10 ma 11 1 01 table 9. port mode register 0 - pmod0 (91h) for at8xc5122 7654 3 210 p3c1 p3c0 p2c1 p2c0 cpresres - p0c1 p0c0 bit number bit mnemonic description 7 - 6 p3c1-p3c0 port 3 configuration bits (applicable to p3.0, p3.1, p3.3, p3.4 only) 00 quasi bi-directional 01 push-pull 10 output low speed 11 input with weak pull-up 5-4 p2c1-p2c0 port 2 configuration bits 00 quasi bi-directional 01 push-pull 10 output low speed 11 input with weak pull-down 3cpresres card presence pull-up resistor cleared to connect the internal pull-up set to disconnect the internal pull-up 2- reserved the value read from this bit is indeterminate. do not set this bit. 1-0 p0c1-p0c0 port 0 configuration bits 00 c51 standard p0 01 reserved 10 output low speed 11 push-pull
18 at8xc5122/23 4202b ? scr ? 07/03 reset value = 00xx 0xxxb reset value = 0000 0000b table 10. port mode register 0 - pmod0 (91h) for at8xc5123 7654 3 210 p3c1 p3c0 - - cpresres - - - bit number bit mnemonic description 7 - 6 p3c1-p3c0 port 3 configuration bits (applicable to p3.0, p3.1, p3.3, p3.4 only) 00 quasi bi-directional 01 push-pull 10 output low speed 11 input with weak pull-up 5-4 reserved the value read from this bit is indeterminate. do not set this bit. 3cpresres card presence pull-up resistor cleared to connect the internal pull-up set to disconnect the internal pull-up 2-0 - reserved the value read from this bit is indeterminate. do not set this bit. table 11. port mode register 1 - pmod1 (84h) for at8xc5122 76543210 p5hc1 p5hc0 p5mc1 p5mc0 p5lc1 p5lc0 p4c1 p4c0 bit number bit mnemonic description 7 - 6 p5hc1-p5hc0 port 5 high configuration bits (applicable from p5.6 to p5.7 only) 00 quasi bi-directional 01 push-pull 10 input with weak pull-down 11 input with weak pull-up 5 - 4 p5mc1-p5mc0 port 5 medium configuration bits (applicable from p5.3 to p5.5 only) 00 quasi bi-directional 01 push-pull 10 input with weak pull-down 11 input with weak pull-up 3 - 2 p5lc1-p5lc0 port 5 low configuration bits (applicable from p5.0 to p5.2 only) 00 quasi bi-directional 01 push-pull 10 input with medium pull-up 11 input with weak pull-up 1 - 0 p4c1-p4c0 port 4 configuration bits (applicable from p4.3 to p4.5 only) 00 quasi bi-directional 01 push-pull 10 output low speed 11 input with medium pull-up
19 at8xc5122/23 4202b ? scr ? 07/03 reset value = xxxx 00xxb reset value = 0000 0000b table 12. port mode register 1 - pmod1 (84h) for at8xc5123 76543210 ----p5lc1p5lc0-- bit number bit mnemonic description 7 - 4 reserved the value read from this bit is indeterminate. do not set this bit. 3 - 2 p5lc1-p5lc0 port 5 low configuration bits (applicable from p5.0 to p5.2 only) 00 quasi bi-directional 01 push-pull 10 input with medium pull-up 11 input with weak pull-up 1 - 0 reserved the value read from this bit is indeterminate. do not set this bit. table 13. led port control register 0 - ledcon0 (f1h) 76543210 led3.1 led3.0 led2.1 led2.0 led1.1 led1.0 led0.1 led0.0 bit number bit mnemonic description 7 - 6 led3 port led3 configuration bits 00 led control disabled 01 2 ma current source when p3.7 is configured as quasi-bi-directional mode 10 4 ma current source when p3.7 is configured as quasi-bi-directional mode 11 10 ma current source when p3.7 is configured as quasi-bidirect. mode 5 - 4 led2 port led2 configuration bits 00 led control disabled 01 2 ma current source when p3.6 is configured as quasi-bi-directional mode 10 4 ma current source when p3.6 is configured as quasi-bi-directional mode 11 10 ma current source when p3.6 is configured as quasi-bidirect. mode 3 - 2 led1 port led1 configuration bits 00 led control disabled 01 2 ma current source when p3.4 is configured as quasi-bi-directional mode 10 4 ma current source when p3.4 is configured as quasi-bi-directional mode 11 10 ma current source when p3.4 is configured as quasi-bidirect. mode 1 - 0 led0 port led0 configuration bits 00 led control disabled 01 2 ma current source when p3.2 is configured as quasi-bi-directional mode 10 4 ma current source when p3.2 is configured as quasi-bi-directional mode 11 10 ma current source when p3.2 is configured as quasi-bidirect. mode
20 at8xc5122/23 4202b ? scr ? 07/03 reset value = 0000 0000b table 14. led port control register 1- ledcon1 (f1h) only for at8xc5122 76543210 - - led6.1 led6.0 led5.1 led5.0 led4.1 led4.0 bit number bit mnemonic description 7 - 6 reserved the value read from this bit is indeterminate. do not set this bit. 5 - 4 led6 port led6 configuration bits 00 led control disabled 01 2 ma current source when p4.5 is configured as quasi-bi-directional mode 10 4 ma current source when p4.5 is configured as quasi-bi-directional mode 11 10 ma current source when p4.5 is configured as quasi-bidirect. mode 3 - 2 led5 port led5 configuration bits 00 led control disabled 01 2 ma current source when p4.4 is configured as quasi-bi-directional mode 10 4 ma current source when p4.4 is configured as quasi-bi-directional mode 11 10 ma current source when p4.4 is configured as quasi-bidirect. mode 1 - 0 led4 port led0 configuration bits 00 led control disabled 01 2 ma current source when p4.3 is configured as quasi-bi-directional mode 10 4 ma current source when p4.3 is configured as quasi-bi-directional mode 11 10 ma current source when p4.3 is configured as quasi-bidirect. mode
21 at8xc5122/23 4202b ? scr ? 07/03 sfr description the special function registers (sfrs) of the at8xc5122/23 fall into the following categories: c51 core registers: acc, b, dph, dpl, psw, sp system configuration registers: pcon, ckrl, ckcon0, ckcon1, cksel, pllcon, plldiv, auxr, auxr1 i/o port registers: p0, p1, p2, p3, p4, p5,pmod1, pmod2 timer registers: tcon, th0, th1, tmod, tl0, tl1 watchdog (wd) registers: wdtrst, wdtprg serial i/o port registers: saddr, saden, sbuf, scon baud rate generator (brg) registers: brl, bdrcon system interrupt registers: ie0, ipl0, iph0, ie1, ipl1, iph1 smart card interface (sci) registers: scsr, sccon/scetu0, scisr/scetu1, scier/sciir, sctbuf/scrbuf, scgt0/scwt0, scgt1/scwt1, scicr/scwt2, sciclk dc/dc converter registers: dcckps keyboard interface registers: kbe, kbf, kbls serial port interface (spi) registers: spcon, spsta, spdat universal serial bus (usb) registers:usbcon, usbaddr, usbint, usbien, uepnum, uepconx, uepstax, ueprst, uepint, uepien, uepdatx, ubyctx, ufnuml, ufnumh led controller registers: ledcon0, ledcon1
22 at8xc5122/23 4202b ? scr ? 07/03 notes: 1. mapping is done using scrs bit in scsr register: if scrs = 0, upper cell, if scrs = 1, lower cell. 2. mapping is done using p/d# bit in pmod0 register : if p/d# = 0, upper cell, if p/d# = 1, lower cell. note: blank: reserved, no write or read is allowed. table 15. at8xc5122 sfr mapping bit addressable not bit addressable 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f f8h uepint 0000 0000 ffh f0h b 0000 0000 ledcon0 0000 0000 f7h e8h p5 1111 1111 efh e0h acc 0000 0000 ledcon1 xx00 0000 ubyctx 0000 0000 e7h d8h dfh d0h psw 0000 0000 rcon xxxx 0xxx uepconx 1000 0000 ueprst 0000 0000 d7h c8h uepstax 0000 0000 uepdatx 0000 0000 cfh c0h p4 1111 1111 scwt3 (1) 0000 0000 uepien 0000 0000 spcon 0001 0100 spsta 0000 0000 spdat 1111 1111 usbaddr 1000 0000 uepnum 0000 0000 c7h sciclk (1) 0x10 1111 b8h ipl0 x000 000 saden 0000 0000 ufnuml 0000 0000 ufnumh 0000 0000 usbcon 0000 0000 usbint 0000 0000 usbien 0000 0000 dcckps 0000 0000 bfh b0h p3 1111 1111 ien1 xxxx x000 ipl1 00xx 00x0 iph1 00xx 00x0 scwt0 (1) 1000 0000 scwt1 (1) 0010 0101 scwt2 (1) 0000 0000 iph0 x000 0000 b7h scgt0 (1) 0000 1100 scgt1 (1) xxxx xxx0 scicr (1) 0000 0000 a8h ien0 0000 0000 saddr 0000 0000 sctbuf (1) 0000 0000 scsr x000 1000 sccon (1) 000 0000 scisr (1) 10x0 0000 sciir (1) 0x00 0000 ckcon1 xxxx xxx0 afh scrbuf (1) 0000 0000 scetu0 (1) 0111 0100 scetu1 (1) xxxx x001 scier (1) 0x00 0000 a0h p2 1111 1111 isel 0000 0100 auxr1 xx1x 0xx0 pllcon xxxx x000 plldiv 0000 0000 wdtrst xxxx xxxx wdtprg xxxx x000 a7h 98h scon 0000 0000 sbuf xxxx xxxx brl 0000 0000 bdrcon xxx0 0000 kbls 0000 0000 kbe 0000 0000 kbf 0000 0000 9fh 90h p1 1111 1111 pmod0 (2) 0000 0000 ckrl xxxx 1111 97h 88h tcon 0000 0000 tmod 0000 0000 tl0 0000 0000 tl1 0000 0000 th0 0000 0000 th1 0000 0000 auxr 0xxx x000 ckcon0 x0x0 x000 8fh 80h p0 1111 1111 sp 0000 0111 dpl 0000 0000 dph 0000 0000 pmod1 0000 0000 cksel xxxx xxx0 pcon 00x1 0000 87h 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f
23 at8xc5122/23 4202b ? scr ? 07/03 notes: 1. mapping is done using scrs bit in scsr register: if scrs = 0, upper cell, if scrs = 1, lower cell. 2. mapping is done using p/d# bit in pmod0 register : if p/d# = 0, upper cell, if p/d# = 1, lower cell. note: blank: reserved, no write or read is allowed. table 16. at8xc5123 sfr mapping bit addressable not bit addressable 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f f8h uepint 0000 0000 ffh f0h b 0000 0000 ledcon0 0000 0000 f7h e8h p5 xxxx xxx1 efh e0h acc 0000 0000 ubyctx 0000 0000 e7h d8h dfh d0h psw 0000 0000 uepconx 1000 0000 ueprst 0000 0000 d7h c8h uepstax 0000 0000 uepdatx 0000 0000 cfh c0h 0 p4 11xx xxxx scwt3 0000 0000 uepien 0000 0000 usbaddr 1000 0000 uepnum 0000 0000 0 c7h 1 sciclk 0x10 1111 1 b8h ipl0 x000 000 saden 0000 0000 ufnuml 0000 0000 ufnumh 0000 0000 usbcon 0000 0000 usbint 0000 0000 usbien 0000 0000 dcckps 0000 0000 bfh b0h 0 p3 1111 1111 ien1 x0xx 0xxx ipl1 x0xx 0xxx iph1 x0xx 0xxx scwt0 (1) 1000 0000 scwt1 (1) 0010 0101 scwt2 (1) 0000 0000 iph0 x000 0000 0 b7h 1 scgt0 (1) 0000 1100 scgt1 (1) xxxx xxx0 scicr (1) 0000 0000 1 a8h 0 ien0 0000 0000 saddr 0000 0000 sctbuf (1) 0000 0000 scsr x000 1000 sccon (1) 000 0000 scisr (1) 10x0 0000 sciir (1) 0x00 0000 ckcon1 xxxx xxx0 0 afh 1 scrbuf (1) 0000 0000 scetu0 (1) 0111 0100 scetu1 (1) xxxx x001 scier (1) 0x00 0000 1 a0h isel 0000 0100 auxr1 xxxx 0xx0 pllcon xxxx x000 plldiv 0000 0000 wdtrst xxxx xxxx wdtprg xxxx x000 a7h 98h scon 0000 0000 sbuf xxxx xxxx brl 0000 0000 bdrcon xxx0 0000 9fh 90h p1 1111 1111 pmod0 (2) 00xx 0xxx ckrl xxxx 1111 97h 88h tcon 0000 0000 tmod 0000 0000 tl0 0000 0000 tl1 0000 0000 th0 0000 0000 th1 0000 0000 auxr 0xxx x000 ckcon0 x0x0 x000 8fh 80h sp 0000 0111 dpl 0000 0000 dph 0000 0000 pmod1 xxxx 00xx cksel xxxx xxx0 pcon 00x1 0000 87h 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f
24 at8xc5122/23 4202b ? scr ? 07/03 note: 1. only for at8xc5122 note: 1. only for at8xc5122 table 17. c51 core registers mnemonicaddname 76543210 acc e0h accumulator acc b f0h b register b psw d0h program status word cy ac f0 rs1 rs0 ov f1 p sp 81h stack pointer sp dpl 82h data pointer low byte (lsb of dptr) dpl dph 83h data pointer high byte (msb of dptr) dph table 18. system configuration registers mnemonicaddname 76 5 43210 pcon 87h power controller smod1 smod0 pof gf1 gf0 pd idl ckcon0 8fh clock controller 0 wdx2 six2 t1x2 t0x2 x2 ckcon1 afh clock controller 1 spix2 cksel 85h clock selection cks ckrl 97h clock reload register ckrel 3-0 pllcon a3h pll controller register ext48 pllen plock plldiv a4h pll divider register r3-0 n3-0 rcon (1) d1h data memory configuration rps auxr 8eh auxiliary register 0 dpu xrs0 extram a0 auxr1 a2h auxiliary register 1 enboot (1) gf3 dps table 19. i/o ports register mnemonic add name 7 6 5 4 3 2 1 0 p0 (1) 80h port 0 p0 p1 90h port 1 p1 p2 (1) a0h port 2 p2 p3 b0h port 3 p3 p4 (1) c0h port 4 p4 p5 e8h port 5 p5(only p5.0 for at8xc5122) pmod0 91h port mode register 0 p3c1 p3c0 p2c1 (1) p2c0 (1) cpresres - p0c1 (1) p0c0 (1) pmod1 84h port mode register 1 p5hc1 (1) p5hc0 (1) p5mc1 (1) p5mc0 (1) p5lc1 p5lc0 p4c1 (1) p4c0 (1)
25 at8xc5122/23 4202b ? scr ? 07/03 note: 1. only for at8xc5122 table 20. timer registers mnemonicaddname 76543210 th0 8ch timer/counter 0 high byte th0 tl0 8ah timer/counter 0 low byte tl0 th1 8dh timer/counter 1 high byte th1 tl1 8bh timer/counter 1 low byte tl1 tcon 88h timer/counter 0 and 1 control tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 tmod 89h timer/counter 0 and 1 modes gate1 c/t1# m11 m01 gate0 c/t0# m10 m00 table 21. watchdog registers mnemonicaddname 76543210 wdtrst a6h watchdog timer reset wdtrst wdtprg a7h watchdog timer program s2-0 table 22. serial i/o port registers mnemonicaddname 76543210 scon 98h serial control fe/sm0 sm1 sm2 ren tb8 rb8 ti ri sbuf 99h serial data buffer sbuf saden b9h slave address mask saden saddr a9h slave address saddr table 23. baud rate generator (brg) registers mnemonicaddname 76543210 brl 9ah baud rate reload brl bdrcon 9bh baud rate control brr tbck rbck spd src table 24. system interrupt registers mnemonicaddname 76543210 ien0 a8h interrupt enable control 0 ea es et1 ex1 et0 ex0 ien1 b1h interrupt enable control 1 eusb esci espi (1) ekb (1) ipl0 b8h interrupt priority control low 0 psl pt1l px1l pt0l px0l iph0 b7h interrupt priority control high 0 psh pt1h px1h pt0h px0h ipl1 b2h interrupt priority control low 1 pusbl pscil pspil (1) pkbl (1) iph1 b3h interrupt priority control high 1 pusbh pscih pspih (1) pkbh (1) isel a1h interrupt enable register cplev presit rxit oelev oeen presen rxen
26 at8xc5122/23 4202b ? scr ? 07/03 note: 1. only for at8xc5122 table 25. smart card interface (sci) registers mnemonicaddname 76543210 scgt0 b4h smart card transmit guard time register 0 gt7 - 0 scgt1 b5h smart card transmit guard time register 1 gt8 scwt0 b4h smart card character/ block wait time register 0 wt7 - 0 scwt1 b5h smart card character/ block wait time register 1 wt15-8 scwt2 b6h smart card character/ block wait time register 2 wt23-16 scwt3 c1h smart card character/ block wait time register 3 wt31-24 scicr b6h smart card interface control register reset carddet vcard1-0 uart wten crep conv sccon ach smart card interface contacts register clk cardc8 cardc4 cardio cardclk cardrst cardvcc scetu0 ach smart card etu register 0 etu7 - 0 scetu1 adh smart card etu register 1 comp etu10-8 scisr adh smart card uart interface status register (read only) sctbe cardin icardovf vcardok scwto sctc scrc scpe sciir aeh smart card uart interrupt identification register (read only) sctbi icarderr vcarderr scwti scti scri scpi scier aeh smart card uart interrupt enable register esctbi icarder evcarder escwti escti escri escpi scsr abh smart card selection register bgten crepsel altkps1-0 scclk1 scrs sctbuf aah smart card transmit buffer register (write only) can store a new byte to be transmitted on the i/o pin when sctbe is set. bit ordering on the i/o pin depends on the convention scrbuf aah smart card receive buffer register (read only) provides the byte received from the i/o pin when scri is set. bit ordering on the i/o pin depends on the convention. sciclk c1h smart card frequency prescaler register xtscs (1) sciclk5-0 table 26. dc/dc converter register mnemonicaddname 76543210 dcckps bfh dc/dc converter reload register mode ovfadj boost[1-0] dcckps3-0 table 27. keyboard interface registers mnemonicaddname 76543210 kbf (1) 9eh keyboard flag register kbe7 - 0 kbe (1) 9dh keyboard input enable register kbf7 - 0
27 at8xc5122/23 4202b ? scr ? 07/03 note: 1. only for at8xc5122 notes: 1. only for at8xc5122 note: 1. only for at8xc5122 kbls (1) 9ch keyboard level selector register kbls7 - 0 table 27. keyboard interface registers mnemonicaddname 76543210 table 28. serial port interface (spi) registers mnemonicaddname 76543210 spcon (1) c3h serial peripheral control spr2 spen ssdis mstr cpol cpha spr1 spr0 spsta (1) c4h serial peripheral status- control spif wcol modf spdat (1) c5h serial peripheral data r7 - 0 table 29. universal serial bus (usb) registers mnemonicaddname 76543210 usbcon bch usb global control usbe suspclk sdrmwup detach uprsm rmwupe confg fadden usbaddr c6h usb address fen uadd6-0 usbint bdh usb global interrupt wupcpu eorint sofint spint usbien beh usb global interrupt enable ewupcpu eeorint esofint espint uepnum c7h usb endpoint number epnum3-0 uepconx d4h usb endpoint x control epen nakien nakout nakin dtgl epdir eptype1 eptype0 uepstax ceh usb endpoint x status dir rxoutb1 stallrq txrdy stl/crc rxsetup rxoutb0 txcmp ueprst d5h usb endpoint reset ep6rst ep5rst ep4rst ep3rst ep2rst ep1rst ep0rst uepint f8h usb endpoint interrupt ep6int ep5int ep4int ep3int ep2int ep1int ep0int uepien c2h usb endpoint interrupt enable ep6inte ep5inte ep4inte ep3inte ep2inte ep1inte ep0inte uepdatx cfh usb endpoint x fifo data fdat7 - 0 ubyctx e2h usb byte counter low (epx) byct6-0 ufnuml bah usb frame number low fnum7 - 0 ufnumh bbh usb frame number high crcok crcerr fnum10-8 table 30. led controller registers mnemonicaddname 76543210 ledcon0 f1h led control 0 led3 led2 led1 led0 ledcon1 (1) e1h led control 1 led6 led5 led4
28 at8xc5122/23 4202b ? scr ? 07/03 clock controller the clock controller is based on an on-chip oscillator feeding an on-chip phase lock loop (pll). all the internal clocks to the peripherals and cpu core are generated by this controller. the at8xc5122/23 xtal1 and xtal2 pins are the input and the output of a single- stage on-chip inverter (see figure 12), which can be configured with off-chip compo- nents as a pierce oscillator (see figure 14). value of capacitors and crystal characteristics are detailed in the section ? dc characteristics ? of the at8xc5122/23 datasheet. the xtal1 pin can also be used as input for an external 48 mhz clock. the clock controller outputs several different clocks as shown in figure 12: a clock for the cpu core a clock for the peripherals which is used to generate the timers, watchdog, spi, uart, and ports sampling clocks. this divided clock will be used to generate the alternate card clock. a clock for the usb a clock for the scib controller a clock for the dc/dc converter these clocks are enabled or not depending on the power reduction mode as detailed in section ? power management ? , page 142. these clocks are generated using four presacalers defined in the table below: prescaler register reload factor function pr1 ckrl ckrl0-3 cpu & peripheral clocks pr2 sciclk sciclk0-5 smart card pr3 scsr altkps0-1 alternate card pr4 dcckps dcckps3:0 dc/dc
29 at8xc5122/23 4202b ? scr ? 07/03 figure 12. oscillator block diagram cpu and peripheral clock two clocks sources are available for cpu and peripherals: ? crystal oscillator on xtal1 and xtal2 pins and a 96 mhz pll (set by sfr to this value). ? external 48 mhz clock on xtal1 pin these clock sources are adapted by the pr1 prescaler to generate the cpu core ck_cpu and the peripheral clocks: ? ck_idle for alternate card and peripherals registers access ? ck_t0 for timer 0 ? ck_t1 for timer 1 ? ck_si for the uart ? ck_wd for the watchdog ? ck_spi for spi xtal1 xtal2 pd pcon.1 pll 96 mhz ext48 pllcon.2 0 1 0 1 cks cksel.0 0 1 x2 ckcon.0 pr1 ckrl.3:0 idl pcon.0 cpu dc/dc pr4 scib pr2 ck_idle alt card pr3 converter 1/2 ck_usb 0 1 usb ck_iso ck_cpu ck_xtal1 ck_pll dcckps.3:0 sciclk5:0 scsr3:2 0 1 periphx2 ckcon0.x or 1 0 x2 ckcon0.0 ck_t0 peripherals ck_t1 ck_si ck_wd ck_spi ck_periph ck_idle ck_idle pllen pllcon.1 ck_xtal1 ck_pll ck_pll ck_xtal1 ck_xtal1 periph = t0, t1, si, wd or spi ckcon1.0 xtscs sciclk.7
30 at8xc5122/23 4202b ? scr ? 07/03 the cpu and peripherals clocks frequencies are defined in the table below. ck_iso and ck_cpu selection two conditions must be present for an optimal work of the scib: ck_cpu > 4/3 * ck_iso and ck_cpu < 6 * ck_iso. if the ck_cpu <= 4/3 * ck_iso, the scib doesn ? t work. if the ck_cpu >= 6* ck_iso, the programmer must take care in three cases: read (or write) operation on a scib register followed immediatly with an other read (or write) operation on the same register. read (or write) operation on a scib register followed immediatly with an other read (or write) operation on a linked register. the list of linked registers is in the table below. write operation on a register of the list below followed immediatly with a read operation on a scib register. to avoid any trouble, a delay must be added between the two accesses on the scib register. the scib must complete the first read (or write) operation before to receive the second. a solution is to add nop (no operation) instructions. the number of nop to add depends of the rate between ck_cpu and ck_iso (see table below). cks x2 f ck_cpu and f ck_idle 00f ck_xtal1 /(2*(16-ckrl)) 01f ck_xtal1 10f ck_pll /(2*(16-ckrl)) 11not allowed linked registers write in scicr and after read of scetu0-1 write in sctbuf and after read of scisr wait after write operation on this registers scicr, scier, scetu0-1,scgt0-1, scwt0-3,sccon min clk_cpu max clk_cpu number of cpu cycles to add clk_cpu >= 6 * clk_iso clk_cpu <= 12 * clk_iso 6 ( example1 nop) clk_cpu >= 12* clk_iso clk_cpu <= 16 * clk_iso 12 ( example 2 nop)
31 at8xc5122/23 4202b ? scr ? 07/03 smart card interface block the smart card interface block (scib) uses two clock trees: ? the first one, ck_idle, is the peripheral clock used for the interface with the microcontroller. ? the second one, ck_iso, is independant from the cpu clock and is generated from the pll output. pr2, a 6-bit prescaler, will be used to generate: 12/9.6/8/6.85/6/5.33/4.8/4.36/ ..../1mhz frequencies. scib clock must be lower than cpu clock. during sci reset, the ck_iso input must be in the range 1 - 5 mhz according to iso 7816. the scib clocks frequency is defined in figure 27: prescaler 2 description and table 37 on page 43. alternate card clock the alternate card uses the peripheral clock divided by the pr3 prescaler. (1; 1/2; 1/4; 1/8 division ratio). see section "alternate card", page 43 for the definition of the alter- nate clock. dc/dc clock the dc/dc block needs a clock with a 50% duty cycle. the frequency must also respect a value between 3.68 mhz and 6mhz. the pr4 prescaler is used to comply with the dc/dc frequency requirement. figure 13. functional block diagram before supplying the dc/dc block, the oscillator clock is adapted to the clock needed by the dc/dc converter. this factor is controlled with the dcckps3:0 register. examples of factors are shown in the following table: xtal1 (mhz) dcckps3:0 value prescaler factor dc/dc converter clk (mhz) 802 4 pr4 fclk_dc/dc fck_xtal1 dcckps3:0
32 at8xc5122/23 4202b ? scr ? 07/03 usb clock the usb interface block use two clock trees: ? the first one is the cpu clock used for the interface with the microcontroller, ck_idle. ? the second one is the usb clock, ck_usb. since the usb frequency must be 48 mhz, a 96 mhz pll with a by 2 divider has to be used. an external frequency can also be used. oscillator two clock sources are available for cpu: crystal oscillator on xtal1 and xtal2 pins: up to 8 mhz external 48 mhz clock on xtal1 pin figure 14. crystal connection pll pll description the at8xc5122 pll is used to generate internal high frequency clock synchronized with an external low-frequency. figure 15 shows the internal structure of the pll. the pfld block is the phase frequency comparator and lock detector. this block makes the comparison between the reference clock coming from the n divider and the reverse clock coming from the r divider and generates some pulses on the up or down signal depending on the edge position of the reverse clock. the pllen bit in pllcon register is used to enable the clock generation. when the pll is locked, the bit plock in pllcon register is set. the chp block is the charge pump that generates the voltage reference for the vco by injecting or extracting charges from the external filter connected on pllf pin (see figure 16). value of the filter components are detailed in the section ? dc characteristics ? . the vco block is the voltage controlled oscillator controlled by the voltage v ref pro- duced by the charge pump. it generates a square wave signal: the pll clock.the ck_pll frequency is defined by the follwing formula: f ck_pll = f ck_xtal1 * (r+1) / (n+1) xtal1 xtal2 8 mhz
33 at8xc5122/23 4202b ? scr ? 07/03 figure 15. pll block diagram and symbol figure 16. pll filter connection pll programming the pll is programmed v ref using the flow showed in figure 17. as soon as clock gen- eration is enabled, user must wait until the lock indicator is set to ensure the clock output is stable. figure 17. pll programming flow pllen pllcon.1 n3:0 n divider r divider vco ck_pll ck_xtal1 pfld plock pllcon.0 pllf chp v ref up down r3:0 vss pllf vss pll programming configure dividers n3:0= xxxxb r3:0= xxxxb enable pll pllen= 1 pll locked? plock= 1?
34 at8xc5122/23 4202b ? scr ? 07/03 registers reset value = xxxx xxx0b reset value = xxxx 1111b reset value = xxxx xxx0b table 31. clock selection register - cksel (s:85h) 76543210 -------cks bit number bit mnemonic description 7:1 - reserved the value read from this bit is indeterminate. do not set this bit. 0cks cpu oscillator select bit set this bit to connect cpu and peripherals to pll output. clear this to to connect cpu and peripherals to xtal1 clock input. table 32. clock reload register - ckrl (s:97h) 76543210 ----ckrl3ckrl2ckrl1ckrl0 bit number bit mnemonic description 7 - 4 - reserved the value read from this bit is indeterminate. do not set this bit. 3:0 ckrl3:0 clock reload register prescaler1 value f ck_cpu =[ 1 / 2*(16-ckrl)] * f ck_xtal1 table 33. clock configuration register 1 - ckcon1 (s:afh) only for at8xc5122 76543210 -------spix2 bit number bit mnemonic description 7 - 4 - reserved the value read from this bit is indeterminate. do not set this bit. 3- reserved the value read from this bit is indeterminate. do not set this bit. 0spix2 spi clock this control bit is validated when the cpu clock x2 is set. when x2 is low, this bit has no effect. cleared to bypass the pr1 prescaler. set to select the pr1 output for this peripheral.
35 at8xc5122/23 4202b ? scr ? 07/03 reset value = x0x0 x000b table 34. clock configuration register 0 - ckcon0 (s:8fh) 76543210 - wdx2 - six2 - t1x2 t0x2 x2 bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6wdx2 watchdog clock this control bit is validated when the cpu clock x2 is set; when x2 is low, this bit has no effect. cleared to bypass the pr1 prescaler. set to select the pr1 output for this peripheral. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4six2 enhanced uart clock (mode 0 and 2) this control bit is validated when the cpu clock x2 is set; when x2 is low, this bit has no effect. cleared to bypass the pr1 prescaler. set to select the pr1 output for this peripheral. 3- reserved the value read from this bit is indeterminate. do not set this bit. 2t1x2 timer 1 clock this control bit is validated when the cpu clock x2 is set; when x2 is low, this bit has no effect. cleared to bypass the pr1 prescaler. set to select the pr1 output for this peripheral. 1t0x2 timer 0 clock this control bit is validated when the cpu clock x2 is set; when x2 is low, this bit has no effect. cleared to bypass the pr1 prescaler. set to select the pr1 output for this peripheral. 0x2 system clock control bit cleared to select the pr1 output for cpu and all the peripherals . set to bypass the pr1 prescaler and to enable the individual peripherals ? x2 ? bits.
36 at8xc5122/23 4202b ? scr ? 07/03 reset value = 0000 0000b reset value = 0000 0000b table 35. pll control register - pllcon (s:a3h) 76543210 -----ext48pllen plock bit number bit mnemonic description 7 - 3 - reserved the value read from these bits is always 0. do not set this bits. 2ext48 external 48 mhz enable bit set this bit to select xtal1 as usb clock. clear this bit to select pll as usb clock. scib clock is controlled by ext48 bit and xtscs bit. 1pllen pll enable bit set to enable the pll. clear to disable the pll. 0plock pll lock indicator set by hardware when pll is locked clear by hardware when pll is unlocked table 36. pll divider register - plldiv (s:a4h) 76543210 r3 r2 r1 r0 n3 n2 n1 n0 bit number bit mnemonic description 7 - 4 r3:0 pll r divider bits 3 - 0 n3:0 pll n divider bits
37 at8xc5122/23 4202b ? scr ? 07/03 smart card interface block (scib) the scib provides all signals to interface directly with a smart card. the compliance with the iso7816, emv ? 2000, gsm and whql standards has been certified. both synchronous (e.g. memory card) and asynchronous smart cards (e.g. micropro- cessor card) are supported. the component supplies the different voltages requested by the smart card. the power off sequence is directly managed by the scib. the card presence switch of the smart card connector is used to detect card insertion or card removal. in case of card removal, the scib de-activates the smart card using the de-activation sequence. an interrupt can be generated when a card is inserted or removed. any malfunction is reported to the microcontroller (interrupt + control register). the different operating modes are configured by internal registers. support of iso/iec 7816 character mode one transmit buffer + one receive buffer 11 bits etu counter 9 bits guard time counter 32 bits waiting time counter auto character repetition on error signal detection in transmit mode auto error signal generation on parity error detection in receive mode power on and power off sequence generation manual mode to drive directly the card i/o
38 at8xc5122/23 4202b ? scr ? 07/03 block diagram the smart card interface block diagram is shown figure 18: figure 18. scib block diagram functional description the architecture of the smart card interface block can be detailed as follows: barrel shifter the barrel shifter allows the translation between 1 bit serial data and 8 bits parallel data the barrel function is useful for character repetition since the character is still present in the shifter at the end of the character transmission. this shifter is able to shift the data in both directions and to invert the input or output value in order to manage both direct and inverse iso7816-3 convention. coupled with the barrel shifter there is a parity checker and generator. there are 2 registers connected to this barrel shifter, one for the transmission and one for the reception. they act as buffers to relieve the cpu of timing constraints. barrel shifter sci registers scart fsm interrupt generator power on power off fsm i/o mux io (in) io (out) clk rst c4 (out) clk_iso c8 (out) clk1 c4 (in) c8 (in) waiting time counter guard time counter vcard int clk_cpu etu counter
39 at8xc5122/23 4202b ? scr ? 07/03 scart fsm (smart card asynchronous receiver transmitter finite state machine) this is the core of the design. its purpose is to control the barrel shifter. to sequence correctly the barrel shifter for a reception or a transmission, it uses the signals issued by the different counters. one of the most important counters is the guard time counter that gives time slots corresponding to the character frame. the scart fsm is enabled only in uart mode. the transition from the receipt mode to the transmit mode is done automatically. priority is given to the transmission. etu counter the etu (elementary timing unit) counter controls the working frequency of the barrel shifter, in fact it generates the enable signal of the barrel shifter. the etu is 11 bits wide and there is a special compensation mode activated with the most significant bit that allows non integer etu value with a working clock equal to the card clock (ck_iso). but the decimal value is limited to a half clock cycle. in fact the bit duration is not fixed. it takes turns in n clock cycles and n-1 clock cycles.the character duration (10 bits) is also equal to 10*(n + 1/2) clock cycles. this allows to reach the required precision of the character duration specified by the iso7816 standard. example: f=372 d=32 => etu=11.625 clock cycles. etu = (etu[10-0] -0.5 * comp) / f iso with etu[10-0] = 12, comp = 1 (bit 7 of scetu1) to achieve this clock rate, we activated the compensation mode and we programmed the etu duration to 12 clock cycles. the result will be a full character duration (10 bits) equal to 11.5 clock cycles. guard time and block guard time counters the minimum time between the leading edge of the start bit of a character and the lead- ing edge of the start bit of the following character transmitted (guard time) is controlled by one counter, as described in figure 19. the minimum time between the leading edge of the start bit of the last received charac- ter and the first character transmitted (block guard time) is controlled by another counter. the bit bgten in scsr register must be set to use this functionality. the transfer of gt[8-0] value to the bgt counter is done on the rising edge of the bgten. they are 9 bits wide and are incremented at the etu rate. figure 19. guard time and block guard time. char 1 char 2 char n char n+1 char n+2 char n+3 < block guard time < guard reception transmission time write ? block guard time ? in gt write ? guard time ? in gt
40 at8xc5122/23 4202b ? scr ? 07/03 figure 20. guard time and block guard time counters waiting time (wt) counter the wt counter is a 32 bits down counter which can be loaded with the value contained in the scwt3, scwt2, scwt1, scwt0 registers. its main purpose is timeout signal generation. it is 32 bits wide and is decremented at the etu rate. the etu counter acts as a prescaler: see figure 21. when the wt counter times out, an interrupt is generated and the scib function is locked: reception and emission are disabled. it can be enabled by resetting the macro or reloading the counter. figure 21. waiting time counter the counter is loaded, if wten = 0, during the write of scwt2 register. this counter is available in both uart and manual modes. but the behavior depends on the selected mode. in manual mode, the wten signal controls the start of the counter (rising edge) and the stop of the counter (falling edge). after a timeout of the counter, a falling edge on wten, a reload of scwt2 and a rising edge of wten are necessary to start again the counter and to release the scib macro. the reload of scwt2 transfers all scwt0, scwt1, scwt2 and scwt3 registers to the wt counter. in uart mode there is an automatic load on the start bit detection. this automatic load is very useful for changing on-the-fly the timeout value since there is a register to hold the load value. that is the case, for example when in t = 1 we have to launch the bwt timeout on the start bit of the last transmitted character. but on the receipt of the first character an other timeout value (cwt) must be used. for this, the new load value of the waiting time counter must be loaded with cwt value before the transmission of the last character. the reload of scwt[3-0] with the new value occurs with wten = 1. after a timeout of the counter in uart mode, the restart is done as in manual mode. the maximum interval between the start leading edge of a character and the start lead- ing edge of the next character is loaded in the scwt3, scwt2, scwt1, scwt0 registers (see figure 21). etu counter block guard time counter timeout scgt1 scgt0 gt[8:0] guard time counter timeout etu counter wt counter timeout scwt2 scwt1 scwt0 wt[31:0] load wten start bit uart write_scwt2 scwt3
41 at8xc5122/23 4202b ? scr ? 07/03 in t=1 mode, the cwt (character waiting time) or the bwt (block waiting time) are loaded in the same registers. the maximum time between two consecutive start bit is wt[31:0] * etu. when used to check bwt according to iso 7816, wt can be set between 971 and 15728651. the wt counter is 32 bits wide in order to handle the bwt extension. in this case, wt must be loaded with the value bwt * wtx. figure 22. t=0 mode figure 23. t=1 mode power-on and power-off fsm in this state, the machine applies the signals on the smart card in accordance with iso7816 standard. to be able to power on the scib, the card presence is mandatory. removal of the smart card will automatically start the power off sequence as described in figure 24. the sci deactivation sequence after a reset of the cpu or after a lost of power supply is iso7816 compliant. the switching order of the signals is the same as in figure 24 but the delay between signals is analog and not clock dependant. char 1 char 2 < wt > gt bloc 1 char 1 char 2 char n bloc 2 char n+1 char n+2 char n+3 < cwt < bwt < cwt transmission reception
42 at8xc5122/23 4202b ? scr ? 07/03 figure 24. sci deactivation sequence after a card extraction interrupt generator there are several sources of interruption but the scib macro-cell issues only one inter- rupt signal: scibit. figure 25. scib interrupt sources this signal is high level active. one of the sources is able to set up the int signal and this is the read of the smart card interrupt register by the cpu that clears this signal. if during the read of the smart card interrupt register an interrupt occurs, the set of the corresponding bit into the smart card interrupt register and the set of the int signal will be delayed after the read access. registers there are fifteen registers to control the scib macro-cell. they are described in table 54 to table 45. some of the register widths are greater than a byte. despite the 8 bits access provided by the biu, the address mapping of this kind of register respects the following rule: the low significant byte register is implemented at the higher address. this implementation makes access to these registers easier when using high level pro- gramming language (c,c++). cvcc crst cclk cio 8 clock cycles esctbi icarder escwti escri escpi evcarder transmit buffer copied to shift register output current out of range output voltage out of range timeout on wt counter complete transmission complete reception parity error detected scib it escti
43 at8xc5122/23 4202b ? scr ? 07/03 additional features clock the ck_iso input must be in the range 1 - 5 mhz according to iso 7816. the ck_iso can be programmed up to 12 mhz. in this case, the timing specification of the output buffer will not comply to iso 7816. figure 26. clock diagram of the scib block figure 27. prescaler 2 description the division factor sciclk must be smaller than 49. if it is greater or equal to 49, the pr2 prescaler is locked. table 37. examples of settings ffor clocks alternate card a second card named ? alternate card ? can be controlled. xtal1 (mhz) ext48 sciclk ck_ iso 48 1 42 4 80 36 4 8 0 44 12 80 42 8 80 40 6 80 24 2 80 0 1 pr2 ck_cpu ck_iso scib fck_pll or fck_idle fck_xtal1 pr2 / (2 * (48 - sciclk[5-0])) ck_iso ext48 pllcon.2 0 1 ck_pll ck_xtal1 xtscs scclk.7 sciclk.[5:0] =48 0 1
44 at8xc5122/23 4202b ? scr ? 07/03 the clock signal cclk1 can be adapted to the xtal frequency. thanks to the clock prescaler which can divide the frequency by 1, 2, 4 or 8. the bits altkps0 and altkps1 in scsr register are used to set this factor. figure 28. alternate card card presence input the internal pull-up (weak pull-up) on card presence input can be disconnected in order to reduce the consumption (cpresres, bit 3 in pmod0). in this case, an external resistor (typically 1 m ? ) must be externally tied to vcc. cpres input can generate an interrupt (see interrupt system section). the detection level can be selected. scib reset the scicr register contains a reset bit. if set, this bit generates a reset of the sci and its registers. table 38 defines the scib registers that are reset and their reset values. table 38. reset values for sci registers sim, sam card alternate card cvcc crst cio cclk fck_idle 1 0 cclk1 scsr reg. pr3 scclk1 1, 1/2, 1/4 or 1/8 p1.7 main card cpres smart card scsr reg. altkps0,1 register name scib reset value (binary) scicr 0000 0000 sccon 0x00 0000 scisr 1000 0000 sciir 0x00 0000 scier 0x00 0000 scsr x000 1000 sctbuf 0000 0000 scrbuf 0000 0000 scetu1, scetu0 xxxx x001, 0111 0100 (372) scgt1, scgt0 0000 0000, 0000 1100 (12) scwt3, scwt2, scwt1, scwt0 0000 0000, 0000 0000, 0010 0101, 1000 0000 (9600) sciclk 0x10 1111
45 at8xc5122/23 4202b ? scr ? 07/03 registers reset value = 0000 0000b table 39. smart card interface control register - scicr (s:b6h, scrs = 1) 76543210 reset carddet vcard1 vcard0 uart wten crep conv bit number bit mnemonic description 7 reset reset set this bit to reset and deactivate the smart card interface. clear this bit to activate the smart card interface. this bit acts as an active high software reset. 6 carddet card presence detector sense clear this bit to indicate the card presence detector is open when no card is inserted (cpres is high). set this bit to indicate the card presence detector is closed when no card is inserted (cpres is low). 5-4 vcard[1:0] card voltage selection: vcard[1] vcard[0] cvcc 0 0 0.0v 0 1 1.8v 1 03.0v 1 1 5.0v 3uart card uart selection clear this bit to use the card i/o bit to drive the card i/o pin. set this bit to use the smart card uart to drive the card i/o pin. controls also the wait time counter as described in section ? waiting time (wt) counter ? , page 40 2wten wait time counter enable clear this bit to stop the counter and enable the load of the wait time counter hold registers. the hold registers are loaded with scwt0, scwt1, scwt2 and scwt3 values when scwt2 is written. set this bit to start the wait time counter. the counters stop when it reaches the timeout value. if the uart bit is set, the wait time counter automatically reloads with the hold registers whenever a start bit is sent or received. 1 crep character repetition clear this bit to disable parity error detection and indication on the card i/o pin in receive mode and to disable character repetition in transmit mode. set this bit to enable parity error indication on the card i/o pin in receive mode and to set automatic character repetition when a parity error is indicated in transmit mode. in receive mode, three times error indication is performed and the parity error flag is set after four times parity error detection. in transmit mode, up to three times character repetition is allowed and the parity error flag is set after five times (reset configuration, can be set at 4 using crepset bit in scsr register) consecutive parity error indication. 0conv iso convention clear this bit to use the direct convention: b0 bit (lsb) is sent first, the parity bit is added after b7 bit and a low level on the card i/o pin represents a ? 0 ? . set this bit to use the inverse convention: b7 bit (lsb) is sent first, the parity bit is added after b0 bit and a low level on the card i/o pin represents a ? 1 ? .
46 at8xc5122/23 4202b ? scr ? 07/03 reset value = 0x00 0000b table 40. smart card contacts register - sccon (s:ach, scrs=0) 76543210 clk - cardc8 cardc4 cardio cardclk cardrst cardvcc bit number bit mnemonic description 7clk card clock selection clear this bit to use the card clk bit (cardclk) to drive card clk pin. set this bit to use xtal or pll signal to drive the card clk pin. note: internal synchronization avoids glitches on the clk pin when switching this bit. 6- reserved the value read from this bit is indeterminate. do not change this bit. 5 cardc8 card c8 clear this bit to drive a low level on the card c8 pin. set this bit to set a high level on the card c8 pin. the cc8 pin can be used as a pseudo bi-directional i/o when this bit is set. 4 cardc4 card c4 clear this bit to drive a low level on the card c4 pin. set this bit to set a high level on the card c4 pin. the cc4 pin can be used as a pseudo bi-directional i/o when this bit is set. 3 cardio card i/o when the uart bit is cleared in registers, the value of this bit is driven to the card i/o pin. then this pin can be used as a pseudo bi-directional i/o when this bit is set. to be used as an input, this bit must contain a 1. 2 cardclk card clk when the clk bit is cleared in sccon register, the value of this bit is driven to the card clk pin. 1 cardrst card rst clear this bit to drive a low level on the card rst pin. set this bit to set a high level on the card rst pin. 0 cardvcc card vcc control clear this bit to desactivate the card interface and set its power-off. the other bits of sccon register have no effect while this bit is cleared. set this bit to power-on the card interface. the activation sequence should be handled by software.
47 at8xc5122/23 4202b ? scr ? 07/03 reset value = 1000 0000b table 41. smart card uart interface status register - scisr (s:adh, scrs=0) 76 5 4 3210 sctbe cardin icardovf vcardok scwto sctc scrc scpe bit number bit mnemonic description 7sctbe scib transmit buffer empty this bit is set by hardware when the transmit buffer is copied to the transmit shift register of the smart card uart. it is cleared by hardware when sctbuf register is written. 6 cardin card presence status this bit is set by hardware if there is a card presence (debouncing filter has to be done by software). this bit is cleared by hardware if there is no card presence. 5 icardovf icc overflow on card this bit is set when the current on card is above the limit specified by bit ovfadj in dcckps register (table 56 on page 56) it is cleared by hardware. 4 vcardok card voltage status this bit is set when the output voltage is within the voltage range specified by vcard field. it is cleared otherwise. 3scwto smart card wait timeout this bit is set by hardware when the smart card waiting time counter expires. it is cleared by the reload of the counter or by the reset of the scib. 2sctc smart card transmitted character this bit is set by hardware when the smart card uart has transmitted a character. it shall be cleared by software after this register is read. 1 scrc smart card received character this bit is set by hardware when the smart card uart has received a character it is cleared by hardware when scbuf register is read. 0scpe smart card parity error this bit is set at the same time as scti or scri if a parity error is detected. it shall be cleared by software after this register is read.
48 at8xc5122/23 4202b ? scr ? 07/03 reset value = 0x00 0000b table 42. smart card uart interrupt identification register (read only) sciir (s:aeh, scrs=0) 765 4 3210 sctbi - icarderr vcarderr scwti scti scri scpi bit number bit mnemonic description 7sctbi scib transmit buffer interrupt this bit is set by hardware when the transmit buffer is copied to the transmit shift register of the smart card uart. it is cleared by hardware when this register is read. 6- reserved the value read from this bit is indeterminate. do not change this bit. 5 icarderr card current status this bit is set when the output current goes out of the current range. it is cleared by hardware when this register is read. 4 vcarderr card voltage status this bit is set when the output voltage goes out of the voltage range specified by vcard field. it is cleared by hardware when this register is read. 3scwti smart card wait timeout interrupt this bit is set by hardware when the smart card timer times out. it is cleared by hardware when this register is read. 2scti smart card transmit interrupt this bit is set by hardware when the smart card uart completes a character transmission. it is cleared by hardware when this register is read. 1 scri smart card receive interrupt this bit is set by hardware when the smart card uart completes a character reception. it is cleared by hardware when this register is read. 0scpi smart card parity error interrupt this bit is set at the same time as scti or scri if a parity error is detected. it is cleared by hardware when this register is read.
49 at8xc5122/23 4202b ? scr ? 07/03 reset value = 0x00 0000b table 43. smart card uart interrupt enable register - scier (s:aeh, scrs=1) 765 4 3210 esctbi - icarder evcarder escwti escti escri escpi bit number bit mnemonic description 7esctbi smart card uart transmit buffer empty interrupt enable clear this bit to disable the smart card uart transmit buffer empty interrupt. set this bit to enable the smart card uart transmit buffer empty interrupt. 6- reserved the value read from this bit is indeterminate. do not change this bit. 5 icarder card current error interrupt enable clear this bit to disable the card current error interrupt. set this bit to enable the card current error interrupt. 4 evcarder card voltage error interrupt enable clear this bit to disable the card voltage error interrupt. set this bit to enable the card voltage error interrupt. 3escwti smart card wait timeout interrupt enable clear this bit to disable the smart card wait timeout interrupt. set this bit to enable the smart card wait timeout interrupt. 2escti smart card transmit interrupt enable clear this bit to disable the smart card uart transmit interrupt. set this bit to enable the smart card uart transmit interrupt. 1 escri smart card receive interrupt enable clear this bit to disable the smart card uart receive interrupt. set this bit to enable the smart card uart receive interrupt. 0escpi smart card parity error interrupt enable clear this bit to disable the smart card uart parity error interrupt. set this bit to enable the smart card uart parity error interrupt.
50 at8xc5122/23 4202b ? scr ? 07/03 reset value = x000 1000b reset value = 0000 0000b table 44. smart card selection register - scsr (s:abh) 76543210 - bgten - crepsel altkps1 altkps0 scclk1 scrs bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not change this bit. 6bgten block guard time enable set this bit to select the minimum interval between the leading edge of the start bits of the last received character and the first character sent in the opposite direction. the transfer of gt[8-0] value to the bgt counter is done on the rising edge of the bgten. clear this bit to suppress the minimum time between reception and transmission. 5- reserved the value read from this bit is indeterminate. do not change this bit. 4 crepsel character repetition selection clear this bit to select 5 times repetition before parity error indication set this bit to select 4 times repetition before parity error indication 3-2 altkps1:0 alternate card clock prescaler factor 00 altkps = 0: prescaler factor equals 1 01 altkps = 1: prescaler factor equals 2 10 altkps = 2: prescaler factor equals 4 (reset value) 11 altkps = 3: prescaler factor equals 8 1 scclk1 alternate card clock selection set to select the prescaled clock (cclk1) clear to select the standard port configuration 0 scrs smart card register selection the scrs bit selects which set of the scib registers is accessed. table 45. smart card transmit buffer register - sctbuf (s:aa, write-only, scrs=0) 76543210 - ------- bit number bit mnemonic description -- can store a new byte to be transmitted on the i/o pin when sctbe is set. bit ordering on the i/o pin depends on the convention.
51 at8xc5122/23 4202b ? scr ? 07/03 reset value = 0000 0000b reset value = 0xxx x001b reset value = 0111 0100b table 46. smart card receive buffer register - scrbuf (s:aa read-only, scrs=1) 76543210 -------- bit number bit mnemonic description -- provides the byte received from the i/o pin when scri is set. bit ordering on the i/o pin depends on the convention. table 47. smart card etu register 1 - scetu1 (s:adh, scrs=1) 76543210 comp - - - - etu10 etu9 etu8 bit number bit mnemonic description 7comp compensation clear this bit when no time compensation is needed (i.e. when the etu to card clk period ratio is close to an integer with an error less than 1/4 of card clk period). set this bit otherwise and reduce the etu period by 1 card clk cycle for even bits. 6-3 - reserved the value read from these bits is indeterminate. do not change these bits. 2-0 etu[10:8] etu msb used together with the etu lsb in scetu0 (table 48) table 48. smart card etu register 0 - scetu0 (s:ach, scrs=1) 76543210 etu7 etu6 etu5 etu4 etu3 etu2 etu1 etu0 bit number bit mnemonic description 7 - 0 etu[7:0] etu lsb the elementary time unit is (etu[10:0] - 0.5*comp)/f, where f is the card clk frequency. according to iso 7816, etu[10:0] can be set between 11 and 2047. the default reset value of etu[10:0] is 372 (f=372, d=1).
52 at8xc5122/23 4202b ? scr ? 07/03 reset value = 0000 1100b reset value = xxxx xxx0b reset value = 0000 0000b table 49. smart card transmit guard time register 0 - scgt0 (s:b4h, scrs=1) 76543210 gt7 gt6 gt5 gt4 gt3 gt2 gt1 gt0 bit number bit mnemonic description 7 - 0 gt[7:0] transmit guard time lsb the minimum time between two consecutive start bits in transmit mode is gt[8:0] * etu. according to iso 7816, gt can be set between 11 and 266 (11 to 254+12 etu). table 50. smart card transmit guard time register 1 - scgt1 (s:b5h, scrs=1) 76543210 -------gt8 bit number bit mnemonic description 7 - 1 - reserved the value read from these bits is indeterminate. do not change these bits. 0gt8 transmit guard time msb used together with the transmit guard time lsb in scgt0 register (table 49). table 51. smart card character/block wait time register 3 scwt3 (s:c1h, scrs=0) 76543210 wt31 wt30 wt29 wt28 wt27 wt26 wt25 wt24 bit number bit mnemonic description 7 - 0 wt[31:24] wait time byte3 used together with wt[23:0] in registers scwt2,scwt1, scwt0 (see table 52).
53 at8xc5122/23 4202b ? scr ? 07/03 reset value = 0000 0000b reset value = 0010 0101b reset value = 1000 0000b table 52. smart card character/block wait time register 2 scwt2 (s:b6h, scrs=0) 76543210 wt23 wt22 wt21 wt20 wt19 wt18 wt17 wt16 bit number bit mnemonic description 7 - 0 wt[23:16] wait time byte2 used together with wt[31:24] and wt[15:0] in registers scwt3,scwt1, scwt0 (see table 54). table 53. smart card character/block wait time register 1 scwt1 (s:b5h, scrs=0) 76543210 wt15 wt14 wt13 wt12 wt11 wt10 wt9 wt8 bit number bit mnemonic description 7 - 0 wt[15:8] wait time byte 1 used together with wt[31:16] and wt[7:0] in registers scwt3,scwt2, scwt0 (see table 51). table 54. smart card character/block wait time register 0 scwt0 (s:b4h, scrs=0) 76543210 wt7 wt6 wt5 wt4 wt3 wt2 wt1 wt0 bit number bit mnemonic description 7 - 0 wt[7:0] wait time byte 0 wt[31:0] is the reload value of the wait time counter wtc . the wtc is a general-purpose timer. it is using the etu clock and is controlled by the wten bit (see table 39 on page 45 and section ? waiting time (wt) counter ? , page 40). when uart bit of registers is set, the wtc is automatically reloaded at each start bit of the uart. it is used to check the maximum time between to consecutive start bits.
54 at8xc5122/23 4202b ? scr ? 07/03 reset value = 0x10 1111b (default value for a divider by two) dc/dc converter the smart card voltage (cvcc) is supplied by the integrated dc/dc converter which is controlled by several registers: the sciir register (table 42 on page 48) controls the cvcc level by means of bits vcard[1:0]. the sccon register (table 40 on page 46) enables to switch the dc/dc converter on or off by means of bit cardvcc. the dcckps register (table 56 on page 56) controls the dc/dc clock and current. the dc/dc converter cannot be switched on while the cpres pin remains inactive. if cpres pin becomes inactive while the dc/dc converter is operating an automatic shut down sequence of the dc/dc converter is initiated by the electronics. it is mandatory to switch off the dc/dc converter before entering in power-down mode. configuration the dc/dc converter can work in two different modes which are selected by bit mode in dcckps register: pump mode: an external inductance of 10 h must be connected between pins li and vcc. vcc can be higher or lower than cvcc. regulator mode: no external inductance is required but vcc must be always higher than cvcc. the dc/dc clock prescaler which is controlled by bits dcckps[3:0], in dcckps regis- ter must be configured to set the dc/dc clock to a working frequency of 4 mhz which depends on the value of the quartz. there is no need to change the default configuration set by the reset sequence if an 8 mhz quartz is used by the application. the dc/dc converter implements a current overflow controller which avoids permanent damage of the dc/dc converter in case of short circuit between cvcc and cvss. the maximum limit is around 100 ma. it is possible to increase this limit in normal operating table 55. smart card clock reload register - sciclk (s:c1h, scrs=1) 76543210 xtscs - sciclk5 sciclk4 sciclk3 sciclk2 sciclk1 sciclk0 bit number bit mnemonic description 7xtscs smart card clock selection bit if xtscs bit is set, xtal1 is scib clock. if xtscs bit is cleared and ext48 bit is set , xtal1 is scib clock. if xtscs bit is cleared and ext48 bit is reset, pll is scib clock. 6- reserved the value read from this bit is indeterminate. do not change these bits. 5 - 0 sciclk5:0 scib clock reload register prescaler 2 reload value is used to defines the card clock frequency. if sciclk5:0 is smaller than 48 fck_iso = fck_pll or fck_xtal1/ (2 * (48 - sciclk5:0)) if sciclk5:0 is equal to 48 fck_iso = fck_xtal1 or fck_xtal1 sciclk5:0 must be smaller than 49.
55 at8xc5122/23 4202b ? scr ? 07/03 mode by 20% by means of bit ovfadj in dcckps register. when the current overflow controller is operating, the icardovf is set by the hardware in scisr register. the current drawn from power supply by the dc/dc converter is controlled during the startup phase in order to avoid high transient current mainly in pump mode which could cause the power supply voltage to drop dramatically. this control is done by means of bits boost[1:0], which increases progressively the startup current level. initialization procedure the initialization procedure is described in flow chart of figure 29. select the cvcc level by means of bits vcard[1:0] in sciir register, set bits boost[1:0] in dcckps register following the current level control wanted. switch the dc/dc on by means of bit cardvcc in sccon register, monitor bit vcardok in scisr register in order to know when the dc/dc converter is ready (cvcc voltage has reached the expected level) figure 29. dc/dc converter initialization procedure while vcc remains higher than 3.6v and startup current lower than 30 ma (depending on the load type), the dc/dc converter should be ready without having to increment boost[1:0]=[0:0] vcardok=1 set timeout to 3 ms timeout expired increment boost [1:0] boost[1:0] is at maximum? dc/dc converter initialization failure end end decrement boost[1:0] to adjust the current overflow
56 at8xc5122/23 4202b ? scr ? 07/03 boost[1:0] bits beyond [0:0] level. if at least one of the two conditions are not met (vcc < 3.6v or startup current > 30 ma), it will be necessary to increment the boost[1:0] bits until the dc/dc converter is ready. incrementation of boost[1:0] bits increases at the same time the current overflow level in the same proportion as the startup current. so once the dc/dc converter is ready it advised to decrement the boost[1:0] bits to restore the overflow current to its normal or desired value. reset value = 0000 0000b table 56. dc/dc converter control register - dcckps (s:bfh) 76543210 mode ovfadj boost1 boost0 dcckps3 dcckps2 dcckps1 dcckps0 bit number bit mnemonic description 7mode regulation mode 0 dc/dc converter (external inductance required) 1 voltage regulator (no external inductance required but vcc > cvcc+0.3v) 6ovfadj current overflow adjustment on smart card terminal 0 normal: 100 ma average 1 normal + 20% 5 - 4 boost[1:0] maximum startup current drawn from power supply 00 normal: 30 ma average 01 normal + 10% 10 normal + 30% 11 normal + 60% current overflow level on smart card terminal 00 normal = ovfadj 01 normal + 10% 10 normal + 30% 11 normal + 60% 3 - 0 dcckps[3:0] dc/dc clock prescaler value 0000 division factor: 2 (reset value) 0001 division factor: 3 0010 division factor: 4 0011 division factor: 5 0100 division factor: 6 0101 division factor: 8 0110 division factor: 10 0111 division factor: 12 1000 division factor: 24 other values reserved
57 at8xc5122/23 4202b ? scr ? 07/03 usb controller the at8xc5122 implements a usb device controller supporting full speed data trans- fer. in addition to the default control endpoint 0, it provides 6 other endpoints, which can be configured in control, bulk, interrupt or isochronous modes: endpoint 0: 32-byte fifo, default control endpoint endpoint 1,2,3: 8-byte fifo endpoint 4,5: 64-byte fifo endpoint 6: 2 x 64-byte ping-pong fifo this allows the firmware to be developed conforming to most usb device classes, for example: usb mass storage class control/bulk/interrupt (cbi) transport, revision 1.0 - december 14, 1998. usb mass storage class bulk-only transport, revision 1.0 - september 31, 1999. usb human interface device class, version 1.1 - april 7, 1999. usb device firmware upgrade class, revision 1.0 - may 13, 1999. usb mass storage classes usb mass storage class cbi transport within the cbi framework, the control endpoint is used to transport command blocks as well as to transport standard usb requests. one bulk-out endpoint is used to transport data from the host to the device. one bulk-in endpoint is used to transport data from the device to the host. and one interrupt endpoint may also be used to signal command completion (protocol 0); it is optional and may not be used (protocol 1). the following configuration adheres to these requirements: endpoint 0: 8 bytes, control in-out endpoint 4: 64 bytes, bulk-out endpoint 5: 64 bytes, bulk-in endpoint 1: 8 bytes, interrupt in usb mass storage class bulk- only transport within the bulk-only framework, the control endpoint is only used to transport class- specific and standard usb requests for device set-up and configuration. one bulk-out endpoint is used to transport commands and data from the host to the device. one bulk- in endpoint is used to transport status and data from the device to the host. no interrupt endpoint is needed. the following configuration adheres to these requirements: endpoint 0: 8 bytes, control in-out endpoint 4: 64 bytes, bulk-out endpoint 5: 64 bytes, bulk-in usb device firmware upgrade (dfu) the usb device firmware update (dfu) protocol can be used to upgrade the on-chip program memory of the at8xc5122. this allows the implementation of product enhancements and patches to devices that are already in the field. two different config- urations and description sets are used to support dfu functions. the run-time configuration co-exists with the usual functions of the device, which may be usb mass storage for the at8xc5122. it is used to initiate dfu from the normal operating mode. the dfu configuration is used to perform the firmware update after device re-configura- tion and usb reset. it excludes any other function. only the default control pipe (endpoint 0) is used to support dfu services in both configurations.
58 at8xc5122/23 4202b ? scr ? 07/03 the only possible value for the wmaxpacketsize in the dfu configuration is 32 bytes, which is the size of the fifo implemented for endpoint 0. description the usb device controller provides the hardware that the at8xc5122 and the at8xc5123 need to interface a usb link to a data flow stored in a double port memory (dpram). the usb controller requires a 48 mhz reference clock, which is the output of the at8xc5122/23 pll (see section "pll", page 32) divided by a clock prescaler. this clock is used to generate a 12 mhz full speed bit clock from the received usb differen- tial data and to transmit data according to full speed usb device tolerance. clock recovery is done by a digital phase locked loop (dpll) block, which is compliant with the jitter specification of the usb bus. the interface engine (sie) block performs nrzi encoding and decoding, bit stuffing, crc generation and checking, and the serial-parallel data conversion. the universal function interface (ufi) performs the interface between the data flow and the dual port ram figure 30. usb device controller block diagram serial interface engine (sie) the sie performs the following functions: nrzi data encoding and decoding. bit stuffing and unstuffing. crc generation and checking. handshakes. token type identifying. address checking. clock generation (via dpll). sie dpll usb d+/d- buffer ufi 12mhz 48 mhz +/- 0.25% d+ up to 48 mhz uc_sysclk c51 microcontroller interface d-
59 at8xc5122/23 4202b ? scr ? 07/03 figure 31. sie block diagram function interface unit (ufi) the function interface unit provides the interface between the at8xc5122 (or at8xc5123) and the sie. it manages transactions at the packet level with minimal inter- vention from the device firmware, which reads and writes the endpoint fifos. figure 32. ufi block diagram end of packet detection start of packet detection d+ d- clock recovery sync detection pid decoder address decoder serial to parallel conversion crc5 & crc16 generation/check usb pattern generator parallel to serial converter bit stuffing nrzi converter crc16 generator nrzi ? nrz bit unstuffing packet bit counter clk48 (48 mhz) sysclk (12 mhz) datain [7:0] dataout 8 8 transfer control fsm dpr control usb side csreg 0 to 7 registers bank dpr control mp side ufi user dpram up to 48 mhz uc_sysclk c51 microcontroller interface asynchronous information transfer endpoint 0 endpoint 1 endpoint 2 endpoint 3 sie dpll endpoint 4 endpoint 5 endpoint 6
60 at8xc5122/23 4202b ? scr ? 07/03 figure 33. minimum intervention from the usb device firmware out transactions: host ufi c51 out data0 (n bytes) ack endpoint fifo read (n bytes) out data1 nack out data1 ack in transactions: host ufi c51 in ack endpoint fifo write in data1 nack interrupt c51 in data1 interrupt c51 endpoint fifo write
61 at8xc5122/23 4202b ? scr ? 07/03 configuration general configuration usb controller enable before any usb transaction, the 48 mhz required by the usb controller must be cor- rectly generated (section "clock controller", page 28). the usb controller should be then enabled by setting the usbe bit in the usbcon register. set address after a reset or a usb reset, the software has to set the fen (function enable) bit in the usbaddr register. this action will allow the usb controller to answer to the requests sent at the address 0. when a set_address request has been received, the usb controller must only answer to the address defined by the request. the new address should be stored in the usbaddr register. the fen bit and the fadden bit in the usbcon register should be set to allow the usb controller to answer only to requests sent at the new address. set configuration the confg bit in the usbcon register should be set after a set_configuration request with a non-zero value. otherwise, this bit should be cleared. endpoint configuration selection of an endpoint the endpoint register access is performed using the uepnum register. the following registers correspond to the endpoint whose number is stored in the uepnum register. to select an endpoint, the firmware has to write the endpoint number in the uepnum register. ? uepstax, ? uepconx, ? uepdatx, ? ubyctx, figure 34. endpoint selection endpoint enable uepnum endpoint 0 endpoint 6 uepsta0 uepcon0 uepdat0 uepsta6 uepcon6 uepdat6 0 1 2 3 4 5 6 sfr registers uepstax uepconx uepdatx x ubyct0 ubyct6 ubyctx
62 at8xc5122/23 4202b ? scr ? 07/03 before using an endpoint, this one should be enabled by setting the epen bit in the uepconx register. an endpoint which is not enabled won ? t answer to any usb request. the default control endpoint (endpoint 0) should always be enabled in order to answer to usb standard requests. endpoint type configuration all standard endpoints can be configured in control, bulk, interrupt or isochronous mode. the ping-pong endpoints can be configured in bulk, interrupt or isochronous mode. the configuration of an endpoint is performed by setting the field eptype with the following values: ? control: eptype = 00b ? isochronous: eptype = 01b ? bulk: eptype = 10b ? interrupt: eptype = 11b the endpoint 0 is the default control endpoint and should always be configured in con- trol type. endpoint direction configuration for bulk, interrupt and isochronous endpoints, the direction is defined with the epdir bit of the uepconx register with the following values: ? in:epdir = 1b ? out:epdir = 0b for control endpoints, the epdir bit has no effect. summary of endpoint configuration: make sure to select the correct endpoint number in the uepnum register before accessing to endpoint specific registers. table 57. summary of endpoint configuration endpoint configuration epen epdir eptype uepconx disabled 0b xb xxb 0xxx xxxb control 1b xb 00b 80h bulk-in 1b 1b 10b 86h bulk-out 1b 0b 10b 82h interrupt-in 1b 1b 11b 87h interrupt-out 1b 0b 11b 83h isochronous-in 1b 1b 01b 85h isochronous-out 1b 0b 01b 81h
63 at8xc5122/23 4202b ? scr ? 07/03 endpoint fifo reset before using an endpoint, its fifo should be reset. this action resets the fifo pointer to its original value, resets the byte counter of the endpoint (ubyctx register), and resets the data toggle bit (dtgl bit in uepconx). the reset of an endpoint fifo is performed by setting to 1 and resetting to 0 the corre- sponding bit in the ueprst register. for example, in order to reset the endpoint number 2 fifo, write 0000 0100b then 0000 0000b in the ueprst register.
64 at8xc5122/23 4202b ? scr ? 07/03 read/write data fifo read data fifo the read access for each out endpoint is performed using the uepdatx register. after a new valid packet has been received on an endpoint, the data are stored into the fifo and the byte counter of the endpoint is updated (ubyctx register). the firmware has to store the endpoint byte counter before any access to the endpoint fifo. the byte counter is not updated when reading the fifo. to read data from an endpoint, select the correct endpoint number in uepnum and read the uepdatx register. this action automatically decreases the corresponding address vector, and the next data is then available in the uepdatx register. write data fifo the write access for each in endpoint is performed using the uepdatx register. to write a byte into an in endpoint fifo, select the correct endpoint number in uep- num and write into the uepdatx register. the corresponding address vector is automatically increased, and another write can be carried out. warning 1: the byte counter is not updated. warning 2: do not write more bytes than supported by the corresponding endpoint. figure 35. endpoint fifo configuration endpoint 0 - bank 0 endpoint 1 - bank 0 endpoint 2 - bank 0 endpoint 3 - bank 0 endpoint 4 - bank 0 endpoint 5 - bank 0 endpoint 6 - bank 0 endpoint 6 - bank 1 8 bytes 32 bytes 8 bytes 8 bytes 64 bytes 2 x 64 bytes base addresses 00h 20h 28h 30h 38h 78h b8h f8h 138h 64 bytes
65 at8xc5122/23 4202b ? scr ? 07/03 bulk / interrupt transactions bulk and interrupt transactions are managed in the same way. bulk/interrupt out transactions in standard mode figure 36. bulk/interrupt out transactions in standard mode an endpoint should be first enabled and configured before being able to receive bulk or interrupt packets. when a valid out packet is received on an endpoint, the rxoutb0 bit is set by the usb controller. this triggers an interrupt if enabled. the firmware has to select the cor- responding endpoint, store the number of data bytes by reading the ubyctx register. if the received packet is a zlp (zero length packet), the ubyctx register value is equal to 0 and no data has to be read. when all the endpoint fifo bytes have been read, the firmware should clear the rxoutb0 bit to allow the usb controller to accept the next out packet on this end- point. until the rxoutb0 bit has been cleared by the firmware, the usb controller will answer a nak handshake for each out requests. if the host sends more bytes than supported by the endpoint fifo, the overflow data won ? t be stored, but the usb controller will consider that the packet is valid if the crc is correct and the endpoint byte counter contains the number of bytes sent by the host. out data0 (n bytes) ack host ufi c51 endpoint fifo read byte 1 out data1 nak rxoutb0 endpoint fifo read byte 2 endpoint fifo read byte n clear rxoutb0 out data1 nak out data1 ack rxoutb0 endpoint fifo read byte 1
66 at8xc5122/23 4202b ? scr ? 07/03 bulk/interrupt out transactions in ping-pong mode (endpoints 6) figure 37. bulk / interrupt out transactions in ping-pong mode an endpoint should be first enabled and configured before being able to receive bulk or interrupt packets. when a valid out packet is received on the endpoint bank 0, the rxoutb0 bit is set by the usb controller. this triggers an interrupt if enabled. the firmware has to select the corresponding endpoint, store the number of data bytes by reading the ubyctx regis- ter. if the received packet is a zlp (zero length packet), the ubyctx register value is equal to 0 and no data has to be read. when all the endpoint fifo bytes have been read, the firmware should clear the rxoub0 bit to allow the usb controller to accept the next out packet on the endpoint bank 0. this action switches the endpoint bank 0 and 1. until the rxoutb0 bit has been cleared by the firmware, the usb controller will answer a nak handshake for each out requests on the bank 0 endpoint fifo. when a new valid out packet is received on the endpoint bank 1, the rxoutb1 bit is set by the usb controller. this triggers an interrupt if enabled. the firmware empties the bank 1 endpoint fifo before clearing the rxoutb1 bit. until the rxoutb1 bit has been cleared by the firmware, the usb controller will answer a nak handshake for each out requests on the bank 1 endpoint fifo. the rxoutb0 and rxoutb1 bits are alternatively set by the usb controller at each new valid packet receipt. the firmware has to clear one of these two bits after having read all the data fifo to allow a new valid packet to be stored in the corresponding bank. a nak handshake is sent by the usb controller only if the banks 0 and 1 has not been released by the firmware. out data0 (n bytes) ack host ufi c51 endpoint fifo bank 0 - read byte 1 rxoutb0 endpoint fifo bank 0 - read byte 2 endpoint fifo bank 0 - read byte n clear rxoutb0 out data1 (m bytes) ack rxoutb1 endpoint fifo bank 1 - read byte 1 endpoint fifo bank 1 - read byte 2 endpoint fifo bank 1 - read byte m clear rxoutb1 out data0 (p bytes) ack rxoutb0 endpoint fifo bank 0 - read byte 1 endpoint fifo bank 0 - read byte 2 endpoint fifo bank 0 - read byte p clear rxoutb0
67 at8xc5122/23 4202b ? scr ? 07/03 if the host sends more bytes than supported by the endpoint fifo, the overflow data won ? t be stored, but the usb controller will consider that the packet is valid if the crc is correct. bulk/interrupt in transactions in standard mode figure 38. bulk/interrupt in transactions in standard mode an endpoint should be first enabled and configured before being able to send bulk or interrupt packets. the firmware should fill the fifo with the data to be sent and set the txrdy bit in the uepstax register to allow the usb controller to send the data stored in fifo at the next in request concerning this endpoint. to send a zero length packet, the firmware should set the txrdy bit without writing any data into the endpoint fifo. until the txrdy bit has been set by the firmware, the usb controller will answer a nak handshake for each in requests. to cancel the sending of this packet, the firmware has to reset the txrdy bit. the packet stored in the endpoint fifo is then cleared and a new packet can be written and sent. when the in packet has been sent and acknowledged by the host, the txcmpl bit in the uepstax register is set by the usb controller. this triggers a usb interrupt if enabled. the firmware should clear the txcmpl bit before filling the endpoint fifo with new data. the firmware should never write more bytes than supported by the endpoint fifo. all usb retry mechanisms are automatically managed by the usb controller. in data0 (n bytes) ack host ufi c51 endpoint fifo write byte 1 in nak txcmpl endpoint fifo write byte 2 endpoint fifo write byte n set txrdy clear txcmpl endpoint fifo write byte 1
68 at8xc5122/23 4202b ? scr ? 07/03 bulk/interrupt in transactions in ping-pong mode figure 39. bulk / interrupt in transactions in ping-pong mode an endpoint will be first enabled and configured before being able to send bulk or inter- rupt packets. the firmware will fill the fifo bank 0 with the data to be sent and set the txrdy bit in the uepstax register to allow the usb controller to send the data stored in fifo at the next in request concerning the endpoint. the fifo banks are automatically switched, and the firmware can immediately write into the endpoint fifo bank 1. when the in packet concerning the bank 0 has been sent and acknowledged by the host, the txcmpl bit is set by the usb controller. this triggers a usb interrupt if enabled. the firmware will clear the txcmpl bit before filling the endpoint fifo bank 0 with new data. the fifo banks are then automatically switched. when the in packet concerning the bank 1 has been sent and acknowledged by the host, the txcmpl bit is set by the usb controller. this triggers a usb interrupt if enabled. the firmware will clear the txcmpl bit before filling the endpoint fifo bank 1 with new data. the bank switch is performed by the usb controller each time the txrdy bit is set by the firmware. until the txrdy bit has been set by the firmware for an endpoint bank, the usb controller will answer a nak handshake for each in requests concerning this bank. note that in the example above, the firmware clears the transmit complete bit (txc- mpl) before setting the transmit ready bit (txrdy). this is done in order to avoid the firmware to clear at the same time the txcmpl bit for bank 0 and the bank 1. the firmware will never write more bytes than supported by the endpoint fifo. in data0 (n bytes) ack host ufi c51 endpoint fifo bank 0 - write byte 1 in nack txcmpl endpoint fifo bank 0 - write byte 2 endpoint fifo bank 0 - write byte n set txrdy endpoint fifo bank 1 - write byte 1 endpoint fifo bank 1 - write byte 2 endpoint fifo bank 1 - write byte m set txrdy in data1 (m bytes) ack endpoint fifo bank 0 - write byte 1 endpoint fifo bank 0 - write byte 2 endpoint fifo bank 0 - write byte p set txrdy clear txcmpl in data0 (p bytes) ack txcmpl clear txcmpl endpoint fifo bank 1 - write byte 1
69 at8xc5122/23 4202b ? scr ? 07/03 control transactions setup stage the dir bit in the uepstax register should be at 0. receiving setup packets is the same as receiving bulk out packets, except that the rxsetup bit in the uepstax register is set by the usb controller instead of the rxoutb0 bit to indicate that an out packet with a setup pid has been received on the control endpoint. when the rxsetup bit has been set, all the other bits of the uep- stax register are cleared and an interrupt is triggered if enabled. the firmware has to read the setup request stored in the control endpoint fifo before clearing the rxsetup bit to free the endpoint fifo for the next transaction. data stage: control endpoint direction the data stage management is similar to bulk management. a control endpoint is managed by the usb controller as a full-duplex endpoint: in and out. all other endpoint types are managed as half-duplex endpoint: in or out. the firmware has to specify the control endpoint direction for the data stage using the dir bit in the uepstax register. if the data stage consists of ins, the firmware has to set the dir bit in the uepstax register before writing into the fifo and sending the data by setting to 1 the txrdy bit in the uepstax register. the in transaction is complete when the txcmpl has been set by the hardware. the firmware should clear the txcmpl bit before any other transaction. if the data stage consists of outs, the firmware has to leave the dir bit at 0. the rxoutb0 bit is set by hardware when a new valid packet has been received on the endpoint. the firmware must read the data stored into the fifo and then clear the rxoutb0 bit to reset the fifo and to allow the next transaction. the bit dir is used to send the correct data toggle in the data stage. to send a stall handshake, see ? stall handshake ? on page 72. status stage the dir bit in the uepstax register should be reset at 0 for in and out status stage. the status stage management is similar to bulk management. for a control write transaction or a no-data control transaction, the status stage consists of a in zero length packet (see ? bulk/interrupt in transactions in standard mode ? on page 67). to send a stall handshake, see ? stall handshake ? on page 72. for a control read transaction, the status stage consists of a out zero length packet (see ? bulk/interrupt out transactions in standard mode ? on page 65).
70 at8xc5122/23 4202b ? scr ? 07/03 isochronous transactions isochronous out transactions in standard mode an endpoint should be first enabled and configured before being able to receive isochro- nous packets. when an out packet is received on an endpoint, the rxoutb0 bit is set by the usb controller. this triggers an interrupt if enabled. the firmware has to select the corre- sponding endpoint, store the number of data bytes by reading the ubyctx register. if the received packet is a zlp (zero length packet), the ubyctx register value is equal to 0 and no data has to be read. the stlcrc bit in the uepstax register is set by the usb controller if the packet stored in fifo has a corrupted crc. this bit is updated after each new packet receipt. when all the endpoint fifo bytes have been read, the firmware should clear the rxoutb0 bit to allow the usb controller to store the next out packet data into the endpoint fifo. until the rxoutb0 bit has been cleared by the firmware, the data sent by the host at each out transaction will be lost. if the rxoutb0 bit is cleared while the host is sending data, the usb controller will store only the remaining bytes into the fifo. if the host sends more bytes than supported by the endpoint fifo, the overflow data won ? t be stored, but the usb controller will consider that the packet is valid if the crc is correct. isochronous out transactions in ping-pong mode an endpoint should be first enabled and configured before being able to receive isochro- nous packets. when a out packet is received on the endpoint bank 0, the rxoutb0 bit is set by the usb controller. this triggers an interrupt if enabled. the firmware has to select the cor- responding endpoint, store the number of data bytes by reading the ubyctx register. if the received packet is a zlp (zero length packet), the ubyctx register value is equal to 0 and no data has to be read. the stlcrc bit in the uepstax register is set by the usb controller if the packet stored in fifo has a corrupted crc. this bit is updated after each new packet receipt. when all the endpoint fifo bytes have been read, the firmware should clear the rxoub0 bit to allow the usb controller to store the next out packet data into the end- point fifo bank 0. this action switches the endpoint bank 0 and 1. until the rxoutb0 bit has been cleared by the firmware, the data sent by the host on the bank 0 endpoint fifo will be lost. if the rxoutb0 bit is cleared while the host is sending data on the endpoint bank 0, the usb controller will store only the remaining bytes into the fifo. when a new out packet is received on the endpoint bank 1, the rxoutb1 bit is set by the usb controller. this triggers an interrupt if enabled. the firmware empties the bank 1 endpoint fifo before clearing the rxoutb1 bit. until the rxoutb1 bit has been cleared by the firmware, the data sent by the host on the bank 1 endpoint fifo will be lost. the rxoutb0 and rxoutb1 bits are alternatively set by the usb controller at each new packet receipt. the firmware has to clear one of these two bits after having read all the data fifo to allow a new packet to be stored in the corresponding bank.
71 at8xc5122/23 4202b ? scr ? 07/03 if the host sends more bytes than supported by the endpoint fifo, the overflow data won ? t be stored, but the usb controller will consider that the packet is valid if the crc is correct. isochronous in transactions in standard mode an endpoint should be first enabled and configured before being able to send isochro- nous packets. the firmware should fill the fifo with the data to be sent and set the txrdy bit in the uepstax register to allow the usb controller to send the data stored in fifo at the next in request concerning this endpoint. if the txrdy bit is not set when the in request occurs, nothing will be sent by the usb controller. when the in packet has been sent, the txcmpl bit in the uepstax register is set by the usb controller. this triggers a usb interrupt if enabled. the firmware should clear the txcmpl bit before filling the endpoint fifo with new data. the firmware should never write more bytes than supported by the endpoint fifo. isochronous in transactions in ping-pong mode an endpoint should be first enabled and configured before being able to send isochro- nous packets. the firmware should fill the fifo bank 0 with the data to be sent and set the txrdy bit in the uepstax register to allow the usb controller to send the data stored in fifo at the next in request concerning the endpoint. the fifo banks are automatically switched, and the firmware can immediately write into the endpoint fifo bank 1. if the txrdy bit is not set when the in request occurs, nothing will be sent by the usb controller. when the in packet concerning the bank 0 has been sent, the txcmpl bit is set by the usb controller. this triggers a usb interrupt if enabled. the firmware should clear the txcmpl bit before filling the endpoint fifo bank 0 with new data. the fifo banks are then automatically switched. when the in packet concerning the bank 1 has been sent, the txcmpl bit is set by the usb controller. this triggers a usb interrupt if enabled. the firmware should clear the txcmpl bit before filling the endpoint fifo bank 1 with new data. the bank switch is performed by the usb controller each time the txrdy bit is set by the firmware. until the txrdy bit has been set by the firmware for an endpoint bank, the usb controller won ? t send anything at each in requests concerning this bank. the firmware should never write more bytes than supported by the endpoint fifo.
72 at8xc5122/23 4202b ? scr ? 07/03 miscellaneous usb reset the eorint bit in the usbint register is set by hardware when a end of reset has been detected on the usb bus. this triggers a usb interrupt if enabled. the usb con- troller is still enabled, but all the usb registers are reset by hardware. the firmware should clear the eorint bit to allow the next usb reset detection. stall handshake this function is only available for control, bulk, and interrupt endpoints. the firmware has to set the stallrq bit in the uepstax register to send a stall handshake at the next request of the host on the endpoint selected with the uepnum register. the rxsetup, txrdy, txcmpl, rxoutb0 and rxoutb1 bits must be first reset to 0. the bit stlcrc is set at 1 by the usb controller when a stall has been sent. this triggers an interrupt if enabled. the firmware should clear the stallrq and stlcrc bits after each stall sent. the stallrq bit is cleared automatically by hardware when a valid setup pid is received on a control type endpoint. start of frame detection the sofint bit in the usbint register is set when the usb controller detects a start of frame pid. this triggers an interrupt if enabled. the firmware should clear the sofint bit to allow the next start of frame detection. frame number when receiving a start of frame, the frame number is automatically stored in the ufnuml and ufnumh registers. the crcok and crcerr bits indicate if the crc of the last start of frame is valid (crcok set at 1) or corrupt (crcerr set at 1). the ufnuml and ufnumh registers are automatically updated when receiving a new start of frame. data toggle bit the data toggle bit is set by hardware when a data 0 packet is received and accepted by the usb controller and cleared by hardware when a data 1 packet is received and accepted by the usb controller. this bit is reset when the firmware resets the endpoint fifo using the ueprst register. for control endpoints, each setup transaction starts with a data 0 and data toggling is then used as for bulk endpoints until the end of the data stage (for a control write transfer). the status stage completes the data transfer with a data 1 (for a control read transfer). for isochronous endpoints, the device firmware should ignore the data-toggle. nak handshakes when a nak handshake is sent by the usb controller to a in or out request from the host, the nakin or nakout bit is set by hardware. this information can be used to determine the direction of the communication during a control transfer. these bits are cleared by software.
73 at8xc5122/23 4202b ? scr ? 07/03 suspend/resume management suspend the suspend state can be detected by the usb controller if all the clocks are enabled and if the usb controller is enabled. the bit spint is set by hardware when an idle state is detected for more than 3 ms. this triggers a usb interrupt if enabled. in order to reduce current consumption, the firmware can put the usb pad in idle mode, stop the clocks and put the c51 in idle or power-down mode. the resume detection is still active. the usb pad is put in idle mode when the firmware clear the spint bit. in order to avoid a new suspend detection 3ms later, the firmware has to disable the usb clock input using the suspclk bit in the usbcon register. the usb pad automatically exits of idle mode when a wake-up event is detected. the stop of the 48 mhz clock from the pll should be done in the following order: 1. disable of the 48 mhz clock input of the usb controller by setting to 1 the sus- pclk bit in the usbcon register. 2. disable the pll by clearing the pllen bit in the pllcon register. resume when the usb controller is in suspend state, the resume detection is active even if all the clocks are disabled and if the c51 is in idle or power-down mode. the wupcpu bit is set by hardware when a non-idle state occurs on the usb bus. this triggers an inter- rupt if enabled. this interrupt wakes up the cpu from its idle or power-down state and the interrupt function is then executed. the firmware will first enable the 48 mhz gener- ation and then reset to 0 the suspclk bit in the usbcon register if needed. the firmware has to clear the spint bit in the usbint register before any other usb operation in order to wake up the usb controller from its suspend mode. the usb controller is then re-activated. figure 40. example of a suspend/resume management usb controller init detection of a suspend state spint set suspclk disable pll microcontroller in power-down detection of a resume state wupcpu enable pll clear suspclk clear wupcpu bit clear spint
74 at8xc5122/23 4202b ? scr ? 07/03 upstream resume a usb device can be allowed by the host to send an upstream resume for remote wake-up purpose. when the usb controller receives the set_feature request: device_remote_wakeup, the firmware should set to 1 the rmwupe bit in the usbcon register to enable this function. rmwupe value should be 0 in the other cases. if the device is in suspend mode, the usb controller can send an upstream resume by clearing first the spint bit in the usbint register and by setting then to 1 the sdrm- wup bit in the usbcon register. the usb controller sets to 1 the uprsm bit in the usbcon register. all clocks must be enabled first. the remote wake is sent only if the usb bus was in suspend state for at least 5 ms. when the upstream resume is com- pleted, the uprsm bit is reset to 0 by hardware. the firmware should then clear the sdrmwup bit. figure 41. example of remote wakeup management usb controller init detection of a suspend state spint set rmwupe suspend management enable clocks upstream resume sent uprsm clear spint set sdmwup clear sdrmwup set_feature: device_remote_wakeup need usb resume uprsm = 1
75 at8xc5122/23 4202b ? scr ? 07/03 detach simulation in order to be re-enumerated by the host, the at8xc5122/23 has the possibility to sim- ulate a detach-attach of the usb bus. the v ref output voltage is between 3.0v and 3.6v. this output can be connected to the d+ pull-up as shown in figure 42. this output can be put in high-impedance when the detach bit is set to 1 in the usbcon register. maintaining this output in high imped- ance for more than 3 s will simulate the disconnection of the device. when resetting the detach bit, an attach is then simulated. the usb controller should be enabled to use this feature. figure 42. example of v ref connection figure 43. disconnect timing d- d+ d- d+ gnd vcc v ref 1.5 k ? usb-b connector 1 2 3 4 d+ d- v ss v il v ihz(min) device disconnected disconnect detected >= 2,5 s
76 at8xc5122/23 4202b ? scr ? 07/03 usb interrupt system interrupt system priorities figure 44. usb interrupt control system interrupt control system as shown in figure 45, many events can produce a usb interrupt: txcmpl: transmitted in data (table 65 on page 83). this bit is set by hardware when the host accept a in packet. rxoutb0: received out data bank 0 (table 65 on page 83). this bit is set by hardware when an out packet is accepted by the endpoint and stored in bank 0. rxoutb1: received out data bank 1 (only for ping-pong endpoints) (table 65 on page 83). this bit is set by hardware when an out packet is accepted by the endpoint and stored in bank 1. rxsetup: received setup (table 65 on page 83). this bit is set by hardware when an setup packet is accepted by the endpoint. nakin and nakout: these bits are set by hardware when a nak handshake has been received on the corresponding endpoint. these bits are cleared by software. stlcrc: stalled (only for control, bulk and interrupt endpoints) (table on page 84). this bit is set by hardware when a stall handshake has been sent as requested by stallrq, and is reset by hardware when a setup packet is received. sofint: start of frame interrupt (table 60 on page 79). this bit is set by hardware when a usb start of frame packet has been received. wupcpu: wake-up cpu interrupt (table 60 on page 79). this bit is set by hardware when a usb resume is detected on the usb bus, after a suspend state. spint: suspend interrupt (table 60 on page 79). this bit is set by hardware when a usb suspend is detected on the usb bus. eusb ien1.6 ea ien0.7 usb controller iph/l interrupt enable lowest priority interrupts priority enable 00 01 10 11 d+ d- table 58. priority levels iphusb iplusb usb priority level 0 0 0 lowest 01 1 10 2 1 1 3 highest
77 at8xc5122/23 4202b ? scr ? 07/03 figure 45. usb interrupt control block diagram txcmp uepstax.0 rxoutb0 uepstax.1 rxsetup uepstax.2 stlcrc uepstax.3 epxie uepien.x epxint uepint.x sofint usbint.3 esofint usbien.3 spint usbint.0 espint usbien.0 eusb ie1.6 endpoint x (x = 0..6) eorint usbint.4 wupcpu usbint.5 ewupcpu usbien.5 rxoutb1 uepstax.6 eeorint usbien.4 nakout uepconx.5 nakin uepconx.4 nakien uepconx.6
78 at8xc5122/23 4202b ? scr ? 07/03 registers reset value = 0000 0000b table 59. usb global control register - usbcon (s:bch) 76 5 43210 usbe suspclk sdrmwup detach uprsm rmwupe confg fadden bit number bit mnemonic description 7usbe usb enable set this bit to enable the usb controller. clear this bit to disable and reset the usb controller, to disable the usb transceiver an to disable the usb controller clock inputs. 6suspclk suspend usb clock set this bit to disable the 48mhz clock input (resume detection is still active). clear this bit to enable the 48mhz clock input. 5sdrmwup send remote wake-up set this bit to force an external interrupt on the usb controller for remote wake up purpose. an upstream resume is send only if the bit rmwupe is set, all usb clocks are enabled and the usb bus was in suspend state for at least 5 ms. see uprsm below. this bit is cleared by software. 4detach detach command set this bit to simulate a detach on the usb line. the v ref pin is then in a floating state. clear this bit to maintain v ref at 3.3v. 3uprsm upstream resume (read only) this bit is set by hardware when sdrmwup has been set and if rmwupe is enabled. this bit is cleared by hardware after the upstream resume has been sent. 2rmwupe remote wake-up enable set this bit to enabled request an upstream resume signaling to the host. clear this bit otherwise. note: do not set this bit if the host has not set the device_remote_wakeup feature for the device. 1confg configured this bit should be set by the device firmware after a set_configuration request with a non-zero value has been correctly processed. it should be cleared by the device firmware when a set_configuration request with a zero value is received. it is cleared by hardware on hardware reset or when an usb reset is detected on the bus (se0 state for at least 32 full speed bit times: typically 2.7 s). 0 fadden function address enable this bit should be set by the device firmware after a successful status phase of a set_address transaction. it should not be cleared afterwards by the device firmware. it is cleared by hardware on hardware reset or when an usb reset is received (see above). when this bit is cleared, the default function address is used (0).
79 at8xc5122/23 4202b ? scr ? 07/03 reset value = 0000 0000b table 60. usb global interrupt register - usbint (s:bdh) 76543210 - - wupcpu eorint sofint - - spint bit number bit mnemonic description 7 - 6 - reserved the value read from these bits is always 0. do not change these bits. 5 wupcpu wake-up cpu interrupt this bit is set by hardware when the usb controller is in suspend state and is re-activated by a non-idle signal from usb line (not by an upstream resume). this triggers a usb interrupt when ewupcpu is set in the table on page 80. when receiving this interrupt, user has to enable all usb clock inputs. this bit should be cleared by software (usb clocks must be enabled before). 4eorint end of reset interrupt this bit is set by hardware when a end of reset has been detected by the usb controller. this triggers a usb interrupt when eeorint is set in the table on page 80. this bit should be cleared by software. 3sofint start of frame interrupt this bit is set by hardware when an usb start of frame pid (sof) has been detected. this triggers a usb interrupt when esofint is set in the table on page 80. this bit should be cleared by software. 2-1 - reserved the value read from these bits is always 0. do not change these bits. 0spint suspend interrupt this bit is set by hardware when a usb suspend (idle bus for three frame periods: a j state for 3 ms) is detected. this triggers a usb interrupt when espint is set in the table on page 80. this bit should be cleared by software before any other usb operation to re- activate the macro.
80 at8xc5122/23 4202b ? scr ? 07/03 reset value = 0001 0000b reset value = 1000 0000b table 61. usb global interrupt enable register - usbien (s:beh) 76 5 43210 - - ewupcpu eeorint esofint - - espint bit number bit mnemonic description 7 - 6 - reserved the value read from these bits is always 0. do not change these bits. 5ewupcpu enable wake-up cpu interrupt set this bit to enable wake-up cpu interrupt. clear this bit to disable wake-up cpu interrupt. 4eeofint enable end of reset interrupt set this bit to enable end of reset interrupt. this bit is set after reset. clear this bit to disable end of reset interrupt. 3esofint enable sof interrupt set this bit to enable sof interrupt. clear this bit to disable sof interrupt. 2-1 - reserved the value read from these bits is always 0. do not change these bits. 0espint enable suspend interrupt set this bit to enable suspend interrupts (see table 60 on page 79). clear this bit to disable suspend interrupts. table 62. usb address register - usbaddr (s:c6h) 76543210 fen uadd6 uadd5 uadd4 uadd3 uadd2 uadd1 uadd0 bit number bit mnemonic description 7fen function enable set this bit to enable the function. fadd is reset to 1. cleared this bit to disable the function. 6-0 uadd[6:0] usb address this field contains the default address (0) after power-up or usb bus reset. it should be written with the value set by a set_address request received by the device firmware.
81 at8xc5122/23 4202b ? scr ? 07/03 reset value = 0000 0000b table 63. usb endpoint number - uepnum (s:c7h) 76543210 ----epnum3epnum2epnum1epnum0 bit number bit mnemonic description 7 - 4 - reserved the value read from these bits is always 0. do not change these bits. 3 - 0 epnum[3:0] endpoint number set this field with the number of the endpoint which should be accessed when reading or writing to, usb byte count register x (x=epnum set in uepnum register) - ubyctx (s:e2h) or usb endpoint x control register - uepconx (s:d4h). this value can be 0, 1, 2, 3, 4, 5 or 6.
82 at8xc5122/23 4202b ? scr ? 07/03 reset value = 1000 0000b when uepnum = 0 reset value = 0000 0000b otherwise table 64. usb endpoint x control register - uepconx (s:d4h) 76543210 epen nakien nakout nakin dtgl epdir eptype1 eptype0 bit number bit mnemonic description 7 epen endpoint enable set this bit to enable the endpoint according to the device configuration. endpoint 0 will always be enabled after a hardware or usb bus reset and participate in the device configuration. clear this bit to disable the endpoint according to the device configuration. 6nakien nak interrupt enable set this bit to enable nakin and nakout interrupt. clear this bit to disable nakin and nakout interrupt. 5nakout nak out sent this bit is set by hardware when the a nak handshake is sent by the usb controller to an out request from the host. this generates an interrupt if the nakien bit is set. this bit shall be cleared by software. 4nakin nak in sent this bit is set by hardware when the a nak handshake is sent by the usb controller to an in request from the host. this generates an interrupt if the nakien bit is set. this bit shall be cleared by software. 3dtgl data toggle (read-only) this bit is set by hardware when a valid data0 packet is received and accepted. this bit is cleared by hardware when a valid data1 packet is received and accepted. 2epdir endpoint direction set this bit to configure in direction for bulk, interrupt and isochronous endpoints. clear this bit to configure out direction for bulk, interrupt and isochronous endpoints. this bit has no effect for control endpoints. 1-0 eptype[1:0] endpoint type set this field according to the endpoint configuration (endpoint 0 will always be configured as control): 00control endpoint 01isochronous endpoint 10bulk endpoint 11interrupt endpoint
83 at8xc5122/23 4202b ? scr ? 07/03 reset value = 0000 0000b table 65. usb endpoint status and control register x - uepstax (s:ceh) x=epnum set in uepnum register) 76543210 dir rxoutb1 stallrq txrdy stl/crc rxsetup rxoutb0 txcmp bit number bit mnemonic description 7dir control endpoint direction this bit is used only if the endpoint is configured in the control type (see ? usb endpoint x control register - uepconx (s:d4h) ? on page 82). this bit determines the control data and status direction. the device firmware should set this bit only for the in data stage, before any other usb operation. otherwise, the device firmware should clear this bit. 6 rxoutb1 received out data bank 1 for endpoint 6 (ping-pong mode) this bit is set by hardware after a new packet has been stored in the endpoint fifo data bank 1 (only in ping-pong mode). then, the endpoint interrupt is triggered if enabled (see ? usb global interrupt register - usbint (s:bdh) ? on page 79) and all the following out packets to the endpoint bank 1 are rejected (nak ? ed) until this bit has been cleared, excepted for isochronous endpoints. this bit should be cleared by the device firmware after reading the out data from the endpoint fifo. 5 stallrq stall handshake request set this bit to request a stall answer to the host for the next handshake. clear this bit otherwise. for control endpoints: cleared by hardware when a valid setup pid is received. 4 txrdy tx packet ready set this bit after a packet has been written into the endpoint fifo for in data transfers. data should be written into the endp oint fifo only after this bit has been cleared. set this bit without writing data to the endpoint fifo to send a zero length packet. this bit is cleared by hardware, as soon as the packet has been sent for isochronous endpoints, or after the host has acknowledged the packet for control, bulk and interrupt endpoints. when this bit is cleared, the endpoint interrupt is triggere d if enabled (see table 60 on page 79). 3stlcrc stall sent / crc error flag - for control, bulk and interrupt endpoints: this bit is set by hardware after a stall handshake has been sent as requested by stallrq. then, the endpoint interrupt is triggered if enabled (see ?? on page 79) it should be cleared by the device firmware. - for isochronous endpoints (read-only) : this bit is set by hardware if the last received data is corrupted (crc error on data). this bit is updated by hardware when a new data is received. 2 rxsetup received setup this bit is set by hardware when a valid setup packet has been received from the host. then, all the other bits of the register are cleared by hardware and the endpoint interrupt is triggered if enabled (see table 60 on page 79). it should be cleared by the device firmware after reading the setup data from the endpoint fifo. 1 rxoutb0 received out data bank 0 (see also rxoutb1 bit for ping-pong endpoints) this bit is set by hardware after a new packet has been stored in the endpoint fifo data bank 0. then, the endpoint interrupt i s triggered if enabled (see ?? on page 79) and all the following out packets to the endpoint bank 0 are rejected (nak ? ed) until this bit has been cleared, excepted for isochronous endpoints. however, for control endpoints, an early setup transaction may overwrite the content of the endpoint fifo, even if its data packet is received while this bit is set. this bit should be cleared by the device firmware after reading the out data from the endpoint fifo. 0txcmpl transmitted in data complete this bit is set by hardware after an in packet has been transmitted for isochronous endpoints and after it has been accepted (ack ? ed) by the host for control, bulk and interrupt endpoints. then, the endpoint interrupt is triggered if enabled (see table 60). this bit should be cleared by the device firmware before setting txrdy.
84 at8xc5122/23 4202b ? scr ? 07/03 reset value = xxxx xxxxb reset value = 0000 0000b table 66. usb fifo data endpoint x (x=epnum set in uepnum register) - uepdatx (s:cfh) 76543210 fdat7 fdat6 fdat5 fdat4 fdat3 fdat2 fdat1 fdat0 bit number bit mnemonic description 7 - 0 fdat [7:0] endpoint x fifo data data byte to be written to fifo or data byte to be read from the fifo, for the endpoint x (see epnum). table 67. usb byte count register x (x=epnum set in uepnum register) - ubyctx (s:e2h) 76543210 - byct6 byct5 byct4 byct3 byct2 byct1 byct0 bit number bit mnemonic description 7- reserved the value read from these bits is always 0. do not change this bit. 6 - 0 byct[6:0] byte count lsb least significant byte of the byte count of a received data packet. this byte count is equal to the number of data bytes received after the data pid.
85 at8xc5122/23 4202b ? scr ? 07/03 reset value = 0000 0000b table 68. usb endpoint fifo reset register - ueprst (s:d5h) 76543210 - ep6rst ep5rst ep4rst ep3rst ep2rst ep1rst ep0rst bit number bit mnemonic description 7- reserved the value read from these bits is always 0. do not change this bit. 6ep6rst endpoint 6 fifo reset set this bit and reset the endpoint fifo prior to any other operation, upon hardware reset or when an usb bus reset has been received. then, clear this bit to complete the reset operation and start using the fifo. 5ep5rst endpoint 5 fifo reset set this bit and reset the endpoint fifo prior to any other operation, upon hardware reset or when an usb bus reset has been received. then, clear this bit to complete the reset operation and start using the fifo. 4ep4rst endpoint 4 fifo reset set this bit and reset the endpoint fifo prior to any other operation, upon hardware reset or when an usb bus reset has been received. then, clear this bit to complete the reset operation and start using the fifo. 3ep3rst endpoint 3 fifo reset set this bit and reset the endpoint fifo prior to any other operation, upon hardware reset or when an usb bus reset has been received. then, clear this bit to complete the reset operation and start using the fifo. 2ep2rst endpoint 2 fifo reset set this bit and reset the endpoint fifo prior to any other operation, upon hardware reset or when an usb bus reset has been received. then, clear this bit to complete the reset operation and start using the fifo. 1ep1rst endpoint 1 fifo reset set this bit and reset the endpoint fifo prior to any other operation, upon hardware reset or when an usb bus reset has been received. then, clear this bit to complete the reset operation and start using the fifo. 0ep0rst endpoint 0 fifo reset set this bit and reset the endpoint fifo prior to any other operation, upon hardware reset or when an usb bus reset has been received. then, clear this bit to complete the reset operation and start using the fifo.
86 at8xc5122/23 4202b ? scr ? 07/03 reset value = 0000 0000b table 69. usb endpoint interrupt register - uepint (s:f8h read-only) 76543210 - ep6int ep5int ep4int ep3int ep2int ep1int ep0int bit number bit mnemonic description 7- reserved the value read from these bits is always 0. do not change this bit. 6ep6int endpoint 6 interrupt this bit is set by hardware when an interrupt is triggered by the (see table 65 on page 83) and this endpoint interrupt is enabled by the uepien register (see table 70 on page 87). this bit is cleared by hardware. 5ep5int endpoint 5 interrupt this bit is set by hardware when an interrupt is triggered by the uepstax register (see table 65 on page 83) and this endpoint interrupt is enabled by the uepien register (see table 70 on page 87). this bit is cleared by hardware. 4ep4int endpoint 4 interrupt this bit is set by hardware when an interrupt is triggered by the uepstax register (see table 65 on page 83) and this endpoint interrupt is enabled by the uepien register (see table 70 on page 87). this bit is cleared by hardware. 3ep3int endpoint 3 interrupt this bit is set by hardware when an interrupt is triggered by the uepstax register (see table 65 on page 83) and this endpoint interrupt is enabled by the uepien register (see table 70 on page 87). this bit is cleared by hardware. 2ep2int endpoint 2 interrupt this bit is set by hardware when an interrupt is triggered by the uepstax register (see table 65 on page 83) and this endpoint interrupt is enabled by the uepien register (see table 70 on page 87). this bit is cleared by hardware. 1ep1int endpoint 1 interrupt this bit is set by hardware when an interrupt is triggered by the uepstax register (see table 65 on page 83) and this endpoint interrupt is enabled by the uepien register (see table 70 on page 87). this bit is cleared by hardware. 0ep0int endpoint 0 interrupt this bit is set by hardware when an interrupt is triggered by the uepstax register (see table on page 83) and this endpoint interrupt is enabled by the uepien register (see table 70 on page 87). this bit is cleared by hardware.
87 at8xc5122/23 4202b ? scr ? 07/03 reset value = 0000 0000b table 70. usb endpoint interrupt enable register - uepien (s:c2h) 76543210 - ep6inte ep5inte ep4inte ep3inte ep2inte ep1inte ep0inte bit number bit mnemonic description 7- reserved the value read from these bits is always 0. do not change this bit. 6ep6inte endpoint 6 interrupt enable set this bit to enable the interrupts for this endpoint. clear this bit to disable the interrupts for this endpoint. 5ep5inte endpoint 5 interrupt enable set this bit to enable the interrupts for this endpoint. clear this bit to disable the interrupts for this endpoint. 4ep4inte endpoint 4 interrupt enable set this bit to enable the interrupts for this endpoint. clear this bit to disable the interrupts for this endpoint. 3ep3inte endpoint 3 interrupt enable set this bit to enable the interrupts for this endpoint. clear this bit to disable the interrupts for this endpoint. 2ep2inte endpoint 2 interrupt enable set this bit to enable the interrupts for this endpoint. clear this bit to disable the interrupts for this endpoint. 1ep1inte endpoint 1 interrupt enable set this bit to enable the interrupts for this endpoint. clear this bit to disable the interrupts for this endpoint. 0ep0inte endpoint 0 interrupt enable set this bit to enable the interrupts for this endpoint. clear this bit to disable the interrupts for this endpoint.
88 at8xc5122/23 4202b ? scr ? 07/03 serial i/o port the serial i/o port in the at8xc5122/23 is compatible with the serial i/o port in the 80c52. the i/o port provides both synchronous and asynchronous communication modes. it operates as an universal asynchronous receiver and transmitter (uart) in three full- duplex modes (modes 1, 2 and 3). asynchronous transmission and reception can occur simultaneously and at different baud rates serial i/o port includes the following enhancements: framing error detection automatic address recognition framing error detection framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). to enable the framing bit error detection feature, set smod0 bit in pcon regis- ter (see figure 46). figure 46. framing error block diagram when this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. an invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two cpus. if a valid stop bit is not found, the framing error bit (fe) in scon register (see figure 51 on page 92) bit is set. software may examine fe bit after each reception to check for data errors. once set, only software or a reset can clear fe bit. subsequently received frames with valid stop bits cannot clear fe bit. when fe feature is enabled, ri rises on stop bit instead of the last data bit (see figure 47 and figure 48). figure 47. uart timings in mode 1 ri ti rb8 tb8 ren sm2 sm1 sm0/fe idl pd gf0 gf1 pof - smod0 smod1 to uart framing error control sm0 to uart mode control (smod0 = 0) set fe bit if stop bit is 0 (framing error) (smod0 = 1) scon (98h) pcon (87h) data byte ri smod0=x stop bit start bit rxd d7 d6 d5 d4 d3 d2 d1 d0 fe smod0=1
89 at8xc5122/23 4202b ? scr ? 07/03 figure 48. uart timings in modes 2 and 3 automatic address recognition the automatic address recognition feature is enabled when the multiprocessor commu- nication feature is enabled (sm2 bit in scon register is set). implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command frame. only when the serial port recognizes its own address, the receiver sets ri bit in scon register to generate an interrupt. this ensures that the cpu is not interrupted by command frames addressed to other devices. if desired, you may enable the automatic address recognition feature in mode 1. in this configuration, the stop bit takes the place of the ninth data bit. bit ri is set only when the received command frame address matches the device ? s address and is terminated by a valid stop bit. to support automatic address recognition, a device is identified by a given address and a broadcast address. note: the multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting sm2 bit in scon register in mode 0 has no effect). given address each device has an individual address that is specified in saddr register; the saden register is a mask byte that contains don ? t care bits (defined by zeros) to form the device ? s given address. the don ? t care bits provide the flexibility to address one or more slaves at a time. the following example illustrates how a given address is formed. to address a device by its individual address, the saden mask byte must be 1111 1111b . for example: saddr0101 0110b saden 1111 1 100b given0101 01xxb the following is an example of how to use given addresses to address different slaves: slave a:saddr1111 0001b saden 1111 1010b given1111 0x0xb slave b:saddr1111 0011b saden 1111 1001b given1111 0xx1b slave c:saddr1111 0010b saden 1111 1 101b given1111 00x1b ri smod0=0 data byte ninth bit stop bit start bit rxd d8 d7 d6 d5 d4 d3 d2 d1 d0 ri smod0=1 fe smod0=1
90 at8xc5122/23 4202b ? scr ? 07/03 the saden byte is selected so that each slave may be addressed separately. for slave a, bit 0 (the lsb) is a don ? t care bit; for slaves b and c, bit 0 is a 1. to commu- nicate with slave a only, the master must send an address where bit 0 is clear (e.g. 1111 0000b ). for slave a, bit 1 is a 1; for slaves b and c, bit 1 is a don ? t care bit. to communicate with slaves b and c, but not slave a, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b ). to communicate with slaves a, b and c, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b ). broadcast address a broadcast address is formed from the logical or of the saddr and saden registers with zeros defined as don ? t care bits, e.g.: saddr0101 0110b saden1111 1 100b broadcast =saddr or saden1111 111xb the use of don ? t care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is ffh. the following is an example of using broadcast addresses: slave a:saddr1111 0001b saden 1111 1010b broadcast1111 1x11b, slave b:saddr1111 0011b saden 1111 1001b broadcast1111 1x11b, slave c:saddr=1111 0010b saden 1111 1 101b broadcast1111 1111b for slaves a and b, bit 2 is a don ? t care bit; for slave c, bit 2 is set. to communicate with all of the slaves, the master must send an address ffh. to communicate with slaves a and b, but not slave c, the master can send and address fbh. reset addresses on reset, the saddr and saden registers are initialized to 00h, i.e. the given and broadcast addresses are xxxx xxxxb (all don ? t care bits). this ensures that the serial port will reply to any address, and so, that it is backwards compatible with the 80c51 microcontrollers that does not support automatic address recognition. timer 1 when using the timer 1, the baud rate is derived from the overflow of the timer. as shown in figure 49 the timer 1 is used in its 8-bit auto-reload mode). smod1 bit in pcon register allows doubling of the generated baud rate.
91 at8xc5122/23 4202b ? scr ? 07/03 figure 49. timer 1 baud rate generator block diagram internal baud rate generator when using the internal baud rate generator, the baud rate is derived from the over- flow of the timer. as shown in figure 50 the internal baud rate generator is an 8-bit auto-reload timer feed by the peripheral clock or by the peripheral clock divided by 6 depending on the spd bit in bdrcon register (see figure 76 on page 98). the internal baud rate generator is enabled by setting bbr bit in bdrcon register. smod1 bit in pcon register allows doubling of the generated baud rate. figure 50. internal baud rate generator block diagram synchronous mode (mode 0) mode 0 is a half-duplex, synchronous mode, which is commonly used to expand the i/0 capabilities of a device with shift registers. the transmit data (txd) pin outputs a set of eight clock pulses while the receive data (rxd) pin transmits or receives a byte of data. the 8-bit data are transmitted and received least-significant bit (lsb) first. shifts occur at a fixed baud rate (see section ? baud rate selection (mode 0) ? ). figure 51 shows the serial port block diagram in mode 0. tr1 tcon.6 0 1 gate1 tmod.7 overflow c/t1# tmod.6 tl1 (8 bits) th1 (8 bits) int1# t1 ck_ t1 / 6 0 1 smod1 pcon.7 / 2 t1 clock to serial port 0 1 overflow spd bdrcon.1 brg (8 bits) brl (8 bits) ck_ si / 6 ibrg clock brr bdrcon.4 0 1 smod1 pcon.7 / 2 to serial port
92 at8xc5122/23 4202b ? scr ? 07/03 figure 51. serial i/o port block diagram (mode 0) transmission (mode 0) to start a transmission mode 0, write to scon register clearing bits sm0, sm1. as shown in figure 52, writing the byte to transmit to sbuf register starts the transmis- sion. hardware shifts the lsb (d0) onto the rxd pin during the first clock cycle composed of a high level then low level signal on txd. during the eighth clock cycle the msb (d7) is on the rxd pin. then, hardware drives the rxd pin high and asserts ti to indicate the end of the transmission. figure 52. transmission waveforms (mode 0) reception (mode 0) to start a reception in mode 0, write to scon register clearing sm0, sm1 and ri bits and setting the ren bit. as shown in figure 53, clock is pulsed and the lsb (d0) is sampled on the rxd pin. the d0 bit is then shifted into the shift register. after eight sampling, the msb (d7) is shifted into the shift register, and hardware asserts ri bit to indicate a completed recep- tion. software can then read the received byte from sbuf register. figure 53. reception waveforms (mode 0) ibrg clock txd rxd sbuf tx sr sbuf rx sr sm1 scon.6 sm0 scon.7 mode decoder m3 m2 m1 m0 mode controller ri scon.0 ti scon.1 ck_ t1 baud rate controller write to sbuf txd rxd ti d0 d1 d2 d3 d4 d5 d6 d7 write to scon txd rxd ri d0 d1 d2 d3 d4 d5 d6 d7 set ren, clear ri
93 at8xc5122/23 4202b ? scr ? 07/03 baud rate selection (mode 0) in mode 0, baud rate can be either fixed or variable. as shown in figure 54, the selection is done using m0src bit in bdrcon register. figure 55 gives the baud rate calculation formulas for each baud rate source. figure 54. baud rate source selection (mode 0) figure 55. baud rate formulas (mode 0) asynchronous modes (modes 1, 2 and 3) the serial port has one 8-bit and two 9-bit asynchronous modes of operation. figure 56 shows the serial port block diagram in such asynchronous modes. figure 56. serial i/o port block diagram (modes 1, 2 and 3) mode 1 mode 1 is a full-duplex, asynchronous mode. the data frame (see figure 57) consists of 10 bits: one start, eight data bits and one stop bit. serial data is transmitted on the txd pin and received on the rxd pin. when a data is received, the stop bit is read in the rb8 bit in scon register. 0 1 m0src bdrcon.0 ck_ si / 6 to serial port ibrg clock baud_rate = 6 (1-spd) ? 32 ? (256 -brl) 2 smod1 ? f ck_si brl = 256 - 6 (1-spd) ? 32 ? baud_rate 2 smod1 ? f ck_si a. fixed formula b. variable formula baud_rate = 6 f ck_si tb8 scon.3 ibrg clock rxd txd sbuf tx sr rx sr sm1 scon.6 sm0 scon.7 mode decoder m3 m2 m1 m0 ri scon.0 ti scon.1 mode & clock controller sbuf rx rb8 scon.2 sm2 scon.4 t1 clock ck_ si
94 at8xc5122/23 4202b ? scr ? 07/03 figure 57. data frame format (mode 1) modes 2 and 3 modes 2 and 3 are full-duplex, asynchronous modes. the data frame (see figure 58) consists of 11 bits: one start bit, eight data bits (transmitted and received lsb first), one programmable ninth data bit and one stop bit. serial data is transmitted on the txd pin and received on the rxd pin. on receive, the ninth bit is read from rb8 bit in scon register. on transmit, the ninth data bit is written to tb8 bit in scon register. alterna- tively, you can use the ninth bit as a command/data flag. figure 58. data frame format (modes 2 and 3) transmission (modes 1, 2 and 3) to initiate a transmission, write to scon register, setting sm0 and sm1 bits according to figure 51 on page 92, and setting the ninth bit by writing to tb8 bit. then, writing the byte to be transmitted to sbuf register starts the transmission. reception (modes 1, 2 and 3) to prepare for a reception, write to scon register, setting sm0 and sm1 bits according to figure 51 on page 92, and setting ren bit. the actual reception is then initiated by a detected high-to-low transition on the rxd pin. framing error detection (modes 1, 2 and 3) framing error detection is provided for the three asynchronous modes. to enable the framing bit error detection feature, set smod0 bit in pcon register as shown in figure 59. when this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. an invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two devices. if a valid stop bit is not found, the software sets fe bit in scon register. software may examine fe bit after each reception to check for data errors. once set, only software or a chip reset clear fe bit. subsequently received frames with valid stop bits cannot clear fe bit. when the framing error detection feature is enabled, ri rises on stop bit instead of the last data bit as detailed in figure 57 and figure 58. figure 59. framing error block diagram mode 1 d0 d1 d2 d3 d4 d5 d6 d7 start bit 8-bit data stop bit modes 2 and 3 d0 d1 d2 d3 d4 d5 d6 d8 start bit 9-bit data stop bit d7 sm0 1 0 smod0 pcon.6 sm0/fe scon.7 framing error controller fe
95 at8xc5122/23 4202b ? scr ? 07/03 baud rate selection (modes 1 and 3) in modes 1 and 3, the baud rate is derived either from the timer 1 or the internal baud rate generator and allows different baud rate in reception and transmission. as shown in figure 60 the selection is done using rbck and tbck bits in bdrcon register. figure 61 gives the baud rate calculation formulas for each baud rate source while table 71 details internal baud rate generator configuration for different peripheral clock frequencies and giving baud rates closer to the standard baud rates. figure 60. baud rate source selection (modes 1 and 3) figure 61. baud rate formulas (modes 1 and 3) 0 1 rbck bdrcon.2 t1 clock to serial ibrg clock reception port 0 1 tbck bdrcon.3 t1 clock to serial ibrg clock transmission port / 16 / 16 baud_rate = 6 (1-spd) ? 32 ? (256 -brl) 2 smod1 ? f ck_si brl = 256 - 6 (1-spd ) ? 32 ? baud_rate 2 smod1 ? f ck_si baud_rate = 6 ? 32 ? (256 -th1) 2 smod1 ? f ck_t1 th1 = 256 - 192 ? baud_rate 2 smod1 ? f ck_t1 a. ibrg formula b. t1 formula
96 at8xc5122/23 4202b ? scr ? 07/03 notes: 1. these frequencies are achieved in x1 mode, f ck_idle = f osc 2. 2. these frequencies are achieved in x2 mode, f ck_idle = f osc . baud rate selection (mode 2) in mode 2, the baud rate can only be programmed to two fixed values: 1/16 or 1/32 of the peripheral clock frequency. as shown in figure 62 the selection is done using smod1 bit in pcon register. figure 63 gives the baud rate calculation formula depending on the selection. figure 62. baud rate generator selection (mode 2) figure 63. baud rate formula (mode 2) for mode 0 for uart, thanks to the bit src located in bdrcon register (table 76) table 71. internal baud rate generator value baud rate f ck_idle = 6 mhz (1) f ck_idle = 8 mhz (1) f ck_idle = 10 mhz (1) spd smod1 brl error% spd smod1 brl error% spd smod1 brl error% 115200 - ----------- 57600 - - - - 1 1 247 3.55 1 1 245 1.36 38400 1 1 246 2.34 1 1 243 0.16 1 1 240 1.73 19200 1 1 236 2.34 1 1 230 0.16 1 1 223 1.36 9600 1 1 217 0.16 1 1 204 0.16 1 1 191 0.16 4800 1 1 178 0.16 1 1 152 0.16 1 1 126 0.16 baud rate f ck_idle = 12 mhz (2) f ck_idle = 16 mhz (2) f ck_idle = 20 mhz (2) spd smod1 brl error% spd smod1 brl error% spd smod1 brl error% 115200 - - - - 1 1 247 3.55 1 1 245 1.36 57600 1 1 243 0.16 1 1 239 2.12 1 1 234 1.36 38400 1 1 236 2.34 1 1 230 0.16 1 1 223 1.36 19200 1 1 217 0.16 1 1 204 0.16 1 1 191 0.16 9600 1 1 178 0.16 1 1 152 0.16 1 1 126 0.16 4800 1 1 100 0.16 1 1 48 0.16 1 0 126 0.16 0 1 smod1 pcon.7 ck_ si / 2 3 16 to serial port baud_rate = 32 2 smod1 ? f ck_si
97 at8xc5122/23 4202b ? scr ? 07/03 registers reset value = 0000 0000b (bit addressable) 76543210 fe/sm0 sm1 sm2 ren tb8 rb8 ti ri bit number bit mnemonic description 7 fe framing error bit (smod0=1 ) clear to reset the error state, not cleared by a valid stop bit. set by hardware when an invalid stop bit is detected. smod0 must be set to enable access to the fe bit sm0 serial port mode bit 0 refer to sm1 for serial port mode selection. smod0 must be cleared to enable access to the sm0 bit 6sm1 serial port mode bit 1 sm0 sm1 mode description baud rate 0 0 0 shift register f ck_idle /6 0 1 1 8-bit uart variable 1 0 2 9-bit uart f ck_idle /32 or /16 1 1 3 9-bit uart variable 5sm2 serial port mode 2 bit/multiprocessor communication enable bit clear to disable multiprocessor communication feature. set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. this bit should be cleared in mode 0. 4ren reception enable bit clear to disable serial reception. set to enable serial reception. 3tb8 transmitter bit 8/ninth bit to transmit in modes 2 and 3. clear to transmit a logic 0 in the 9th bit. set to transmit a logic 1 in the 9th bit. 2rb8 receiver bit 8/ninth bit received in modes 2 and 3 cleared by hardware if 9th bit received is a logic 0. set by hardware if 9th bit received is a logic 1. in mode 1, if sm2 = 0, rb8 is the received stop bit. in mode 0 rb8 is not used. 1ti transmit interrupt flag clear to acknowledge interrupt. set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes. 0ri receive interrupt flag clear to acknowledge interrupt. set by hardware at the end of the 8th bit time in mode 0, see figure 47 and figure 48 in the other modes.
98 at8xc5122/23 4202b ? scr ? 07/03 reset value = 0000 0000b reset value = 0000 0000b reset value = xxxx xxxxb reset value = 0000 0000b table 76. baud rate control register - bdrcon - (9bh) reset value = xxx0 0000b (not bit addressable) table 72. slave address mask register for uart - saden (b9h) 76543210 table 73. slave address register for uart - saddr (a9h) 76543210 table 74. serial buffer register for uart - sbuf (99h) 76543210 table 75. baud rate reload register for the internal baud rate generator, uart - brl (9ah) 76543210 7 6 5 4 3 2 1 0 - - - brr tbck rbck spd src b it number bit mnemonic description 7 - 5 - reserved the value read from this bit is indeterminate. do not change these bits. 4brr baud rate run control bit cleared to stop the internal baud rate generator. set to start the internal baud rate generator. 3tbck transmission baud rate generator selection bit for uart cleared to select timer 1 or timer 2 for the baud rate generator. set to select internal baud rate generator. 2rbck reception baud rate generator selection bit for uart cleared to select timer 1 or timer 2 for the baud rate generator. set to select internal baud rate generator. 1spd baud rate speed control bit for uart cleared to select the slow baud rate generator. set to select the fast baud rate generator. 0src baud rate source select bit in mode 0 for uart cleared to select f osc /12 as the baud rate generator (f cl_idle /6 in x2 mode). set to select the internal baud rate generator for uarts in mode 0.
1 at8xc5122/23 4202b ? scr ? 07/03 serial port interface (spi) only for at8xc5122. the serial peripheral interface module (spi) which allows full-duplex, synchronous, serial communication between the mcu and peripheral devices, including other mcus. features features of the spi module include the following: full-duplex, three-wire synchronous transfers master or slave operation eight programmable master clock rates serial clock with programmable polarity and phase master mode fault error flag with mcu interrupt capability write collision flag protection signal description figure 64 shows a typical spi bus configuration using one master controller and many slave peripherals. the bus is made of three wires connecting all the devices: figure 64. typical spi bus the master device selects the individual slave devices by using four pins of a parallel port to control the four ss pins of the slave devices. master output slave input (mosi) this 1-bit signal is directly connected between the master device and a slave device. the mosi line is used to transfer data in series from the master to the slave. therefore, it is an output signal from the master, and an input signal to a slave. a byte (8-bit word) is transmitted most significant bit (msb) first, least significant bit (lsb) last. master input slave output (miso) this 1-bit signal is directly connected between the slave device and a master device. the miso line is used to transfer data in series from the slave to the master. therefore, it is an output signal from the slave, and an input signal to the master. a byte (8-bit word) is transmitted most significant bit (msb) first, least significant bit (lsb) last. spi serial clock (sck) this signal is used to synchronize the data movement both in and out the devices through their mosi and miso lines. it is driven by the master for eight clock cycles which allows to exchange one byte on the serial lines. slave 1 miso mosi sck ss miso mosi sck ss 0 1 2 3 slave 3 slave 4 miso mosi sck ss slave 2 vdd master port miso mosi sck ss miso mosi sck ss
2 at8xc5122/23 4202b ? scr ? 07/03 slave select (ss ) each slave peripheral is selected by one slave select pin (ss ). this signal must stay low for any message for a slave. only one master (ss high level) can drive the network. the master may select each slave device by software through port pins (figure 64). to prevent bus conflicts on the miso line, only one slave should be selected at a time by the master for a transmission. in a master configuration, the ss line can be used in conjunction with the modf flag in the spi status register (spsta) to prevent multiple masters from driving mosi and sck (see section ? error conditions ? , page 6). a high level on the ss pin puts the miso line of a slave spi in a high-impedance state. the ss pin could be used as a general-purpose if the following conditions are met: the device is configured as a master and the ssdis control bit in spcon is set. this kind of configuration can be found when only one master is driving the network and there is no way that the ss pin will be pulled low. therefore, the modf flag in the spsta will never be set (1) . the device is configured as a slave with cpha and ssdis control bits set (2) . this kind of configuration can happen when the system comprises one master and one slave only. therefore, the device should always be selected and there is no reason that the master uses the ss pin to select the communicating slave device. baud rate in master mode, the baud rate can be selected from a baud rate generator which is con- troled by three bits in the spcon register: spr2, spr1 and spr0. the master clock is chosen from one of six clock rates resulting from the division of the internal clock by 4, 8, 16, 32, 64 or 128. table 77 gives the different clock rates selected by spr2:spr1:spr0 table 77. spi master baud rate selection 1. clearing ssdis control bit does not clear modf. 2. special care should be taken not to set ssdis control bit when cpha = ? 0 ? because in this mode, the ss is used to start the transmission. spr2:spr1:spr0 clock rate baud rate divisor (bd) 000 reserved n/a 001 f ck_spi /4 4 010 f ck_spi / 8 8 011 f ck_spi /16 16 100 f ck_spi /32 32 101 f ck_spi /64 64 110 f ck_spi /128 128 111 reserved n/a
3 at8xc5122/23 4202b ? scr ? 07/03 functional description figure 65 shows a detailed structure of the spi module. figure 65. spi module block diagram operating modes the serial peripheral interface can be configured as one of the two modes: master mode or salve mode. the configuration and initialization of the spi module is made through one register: the serial peripheral control register (spcon) once the spi is configured, the data exchange is made using: spcon the serial peripheral status register (spsta) the serial peripheral data register (spdat) during an spi transmission, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). a serial clock line (sck) synchronizes shifting and sam- pling on the two serial data lines (mosi and miso). a slave select line (ss ) allows individual selection of a slave spi device; slave devices that are not selected do not interfere with spi bus activities. when the master device transmits data to the slave device via the mosi line, the slave device responds by sending data to the master device via the miso line. this implies full-duplex transmission with both data out and data in synchronized with the same clock (figure 66). shift register 0 1 2 3 4 5 6 7 internal bus pin control logic miso mosi sck m s clock logic clock divider clock select /4 /64 /128 spi interrupt request 8-bit bus 1-bit signal ss intclk /32 /8 /16 receive data register spdat spi control spsta cpha spr0 spr1 cpol mstr ssdis spen spr2 spcon wcol modf spif - ----
4 at8xc5122/23 4202b ? scr ? 07/03 figure 66. full-duplex master-slave interconnection master mode the spi operates in master mode when the master bit, mstr (1) , in the spcon register is set. only one master spi device can initiate transmissions. software begins the trans- mission from a master spi module by writing to the serial peripheral data register (spdat). if the shift register is empty, the byte is immediately transferred to the shift register. the byte begins shifting out on mosi pin under the control of the serial clock, sck. simultaneously, another byte shifts in from the slave on the master ? s miso pin. the transmission ends when the serial peripheral transfer data flag, spif, in spsta becomes set. at the same time that spif becomes set, the received byte from the slave is transferred to the receive data register in spdat. software clears spif by reading the serial peripheral status register (spsta) with the spif bit set, and then reading the spdat. when the pin ss is pulled down during a transmission, the data is interrupted and when the transmission is established again, the data present in the spdat is resent. slave mode the spi operates in slave mode when the master bit, mstr (2) , in the spcon register is cleared. before a data transmission occurs, the slave select pin, ss , of the slave device must be set to ? 0 ? . ss must remain low until the transmission is complete. in a slave spi module, data enters the shift register under the control of the sck from the master spi module. after a byte enters the shift register, it is immediately transferred to the receive data register in spdat, and the spif bit is set. to prevent an overflow condition, slave software must then read the spdat before another byte enters the shift register (3) . a slave spi must complete the write to the spdat (shift register) at least one bus cycle before the master spi starts a transmission. if the write to the data register is late, the spi transmits the data already in the shift register from the previous transmission. transmission formats software can select any of four combinations of serial clock (sck) phase and polarity using two bits in the spcon: the clock polarity (cpol (4) ) and the clock phase (cpha (4) ). cpol defines the default sck line level in idle state. it has no significant effect on the transmission format. cpha defines the edges on which the input data are sampled and the edges on which the output data are shifted (figure 67 and figure 68). the clock phase and polarity should be identical for the master spi device and the com- municating slave device. 8-bit shift register spi clock generator master mcu 8-bit shift register miso miso mosi mosi sck sck vss vdd ss ss slave mcu 1. the spi module should be configured as a master before it is enabled (spen set). also the master spi should be configured before the slave spi. 2. the spi module should be configured as a slave before it is enabled (spen set). 3. the maximum frequency of the sck for an spi configured as a slave is the bus clock speed. 4. before writing to the cpol and cpha bits, the spi should be disabled (spen = ? 0 ? ).
5 at8xc5122/23 4202b ? scr ? 07/03 figure 67. data transmission format (cpha = 0) figure 68. data transmission format (cpha = 1) as shown in figure 67, the first sck edge is the msb capture strobe. therefore the slave must begin driving its data before the first sck edge, and a falling edge on the ss pin is used to start the transmission. the ss pin must be toggled high and then low between each byte transmitted (figure 69). figure 69. cpha/ss timing figure 68 shows an spi transmission in which cpha is ? 1 ? . in this case, the master begins driving its mosi pin on the first sck edge. therefore, the slave uses the first sck edge as a start transmission signal. the ss pin can remain low between transmis- sions (figure 69). this format may be preferable in systems having only one master and only one slave driving the miso data line. msb bit6 bit5 bit4 bit3 bit2 bit1 lsb bit6 bit5 bit4 bit3 bit2 bit1 msb lsb 13 245678 capture point ss (to slave) miso (from slave) mosi (from master) sck (cpol = 1) sck (cpol = 0) spen (internal) sck cycle number msb bit6 bit5 bit4 bit3 bit2 bit1 lsb bit6 bit5 bit4 bit3 bit2 bit1 msb lsb 13 2 45678 capture point ss (to slave) miso (from slave) mosi (from master) sck (cpol = 1) sck (cpol = 0) spen (internal) sck cycle number byte 1 byte 2 byte 3 miso/mosi master ss slave ss (cpha = 1) slave ss (cpha = 0)
6 at8xc5122/23 4202b ? scr ? 07/03 error conditions the following flags in the spsta signal spi error conditions. mode fault (modf) modf error bit in master mode spi indicates that the level on the slave select (ss ) pin is inconsistent with the actual mode of the device. modf is set to warn that there may have a multi-master conflict for system control. in this case, the spi system is affected in the following ways: an spi receiver/error cpu interrupt request is generated. the spen bit in spcon is cleared. this disable the spi. the mstr bit in spcon is cleared. when ss disable (ssdis) bit in the spcon register is cleared, the modf flag is set when the ss signal becomes ? 0 ? . however, as stated before, for a system with one master, if the ss pin of the master device is pulled low, there is no way that another master is attempting to drive the net- work. in this case, to prevent the modf flag from being set, software can set the ssdis bit in the spcon register and therefore making the ss pin as a general-purpose i/o pin. clearing the modf bit is accomplished by a read of spsta register with modf bit set, followed by a write to the spcon register. spen control bit may be restored to its orig- inal set state after the modf bit has been cleared. write collision (wcol) a write collision (wcol) flag in the spsta is set when a write to the spdat register is done during a transmit sequence. wcol does not cause an interruption, and the transfer continues uninterrupted. clearing the wcol bit is done through a software sequence of an access to spsta and an access to spdat. overrun condition an overrun condition occurs when the master device tries to send several data bytes and the slave device has not cleared the spif bit issuing from the previous data byte transmitted. in this case, the receiver buffer contains the byte sent after the spif bit was last cleared. a read of the spdat returns this byte. all others bytes are lost. this condition is not detected by the spi peripheral. ss error flag ( sserr ) a synchronous serial slave error occurs when ss goes high before the end of a received data in slave mode. sserr does not cause in interruption, this bit is cleared by writing 0 to spen bit ( reset of the spi state machine ). interrupts two spi status flags can generate a cpu interrupt requests: table 78. spi interrupts serial peripheral data transfer flag, spif: this bit is set by hardware when a transfer has been completed. spif bit generates transmitter cpu interrupt requests. mode fault flag, modf: this bit becomes set to indicate that the level on the ss is inconsistent with the mode of the spi. modf with ssdis reset, generates receiver/error cpu interrupt requests. flag request spif (sp data transfer) spi transmitter interrupt request modf (mode fault) spi receiver/error interrupt request (if ssdis = ? 0 ? )
7 at8xc5122/23 4202b ? scr ? 07/03 figure 70 gives a logical view of the above statements. figure 70. spi interrupt requests generation registers there are three registers in the module that provide control, status and data storage functions. these registers are describes in the following paragraphs. serial peripheral control register (spcon) the serial peripheral control register does the following: selects one of the master clock rates configures the spi module as master or slave selects serial clock polarity and phase enables the spi module frees the ss pin for a general-purpose ssdis modf cpu interrupt request spi receiver/error cpu interrupt request spi transmitter spi cpu interrupt request spif
8 at8xc5122/23 4202b ? scr ? 07/03 reset value = 00010100b table 79. serial peripheral control register - spcon (c3h) 76543210 spr2 spen ssdis mstr cpol cpha spr1 spr0 bit number bit mnemonic r/w mode description 7spr2rw serial peripheral rate 2 bit with spr1 and spr0 define the clock rate 6 spen rw serial peripheral enable clear to disable the spi interface (internal reset of the spi) set to enable the spi interface 5ssdisrw ss disable clear to enable ss in both master and slave modes set to disable ss in both master and slave modes. in slave mode, this bit has no effect if cpha = ? 0 ? 4mstrrw serial peripheral master clear to configure the spi as a slave set to configure the spi as a master 3cpolrw clock polarity clear to have the sck set to ? 0 ? in idle state set to have the sck set to ? 1 ? in idle low 2cpharw clock phase clear to have the data sampled when the spsck leaves the idle state (see cpol) set to have the data sampled when the spsck returns to idle state (see cpol) 1spr1rw serial peripheral rate (spr2:spr1:spr0) 000: reserved 001: f ck_spi /4 010: f ck_spi /8 011: f ck_spi /16 0spr0rw 100: f ck_spi /32 101: f ck_spi /64 110: f ck_spi /128 111: reserved
9 at8xc5122/23 4202b ? scr ? 07/03 serial peripheral status register (spsta) the serial peripheral status register contains flags to signal the following conditions: data transfer complete write collision inconsistent logic level on ss pin (mode fault error) reset value = 00x0xxxxb table 80. serial peripheral status and control register - spsta (c4h) 76543210 spifwcolsserrmodf---- bit number bit mnemonic r/w mode description 7spifr serial peripheral data transfer flag clear by hardware to indicate data transfer is in progress or has been approved by a clearing sequence. set by hardware to indicate that the data transfer has been completed. 6wcolr write collision flag cleared by hardware to indicate that no collision has occurred or has been approved by a clearing sequence. set by hardware to indicate that a collision has been detected. 5 sserr r synchronous serial slave error flag set by hardware when ss is modified before the end of a received data. cleared by disabling the spi (clearing spen bit in spcon). 4modfr mode fault cleared by hardware to indicate that the ss pin is at appropriate logic level, or has been approved by a clearing sequence. set by hardware to indicate that the ss pin is at inappropriate logic level 3 - 0 - rw reserved the value read from this bit is indeterminate. do not change these bits.
10 at8xc5122/23 4202b ? scr ? 07/03 serial peripheral data register (spdat) the serial peripheral data register (table 81) is a read/write buffer for the receive data register. a write to spdat places data directly into the shift register. no transmit buffer is available in this model. a read of the spdat returns the value located in the receive buffer and not the content of the shift register. reset value = xxxx xxxxb table 81. serial peripheral data register - spdat (c5h) 76543210 r7 r6 r5 r4 r3 r2 r1 r0 bit number bit mnemonic description 7-0 r7:0 receive data bits spcon, spsta and spdat registers may be read and written at any time while there is no on-going exchange. however, special care should be taken when writing to them while a transmission is on-going: do not change spr2, spr1 and spr0 do not change cpha and cpol do not change mstr clearing spen would immediately disable the peripheral writing to the spdat will cause an overflow
109 at8xc5122/23 4202b ? scr ? 07/03 timers/counters the at8xc5122 implements two general-purpose, 16-bit timers/counters. although they are identified as timer 0, timer 1, you can independently configure each to operate in a variety of modes as a timer or as an event counter. when operating as a timer, a timer/counter runs for a programmed length of time, then issues an interrupt request. when operating as a counter, a timer/counter counts negative transitions on an exter- nal pin. after a preset number of counts, the counter issues an interrupt request. the timer registers and associated control registers are implemented as addressable special function registers (sfrs). two of the sfrs provide programmable control of the timers as follows: timer/counter mode control register (tmod) and timer/counter control register (tcon) control respectively timer 0 and timer 1. the various operating modes of each timer/counter are described below. timer/counter operations for example, a basic operation is timer registers thx and tlx (x= 0, 1) connected in cascade to form a 16-bit timer. setting the run control bit (trx) in the tcon register (see table 82 on page 114) turns the timer on by allowing the selected input to incre- ment tlx. when tlx overflows, it increments thx and when thx overflows it sets the timer overflow flag (tfx) in the tcon register. setting the trx does not clear the thx and tlx timer registers. timer registers can be accessed to obtain the current count or to enter preset values. they can be read at any time but the trx bit must be cleared to preset their values, otherwise the behavior of the timer/counter is unpredictable. the c/tx# control bit selects timer operation or counter operation by selecting the divided-down system clock or the external pin tx as the source for the counted signal. the trx bit must be cleared when changing the operating mode, otherwise the behavior of the timer/counter is unpredictable. for timer operation (c/tx#= 0), the timer register counts the divided-down system clock. the timer register is incremented once every peripheral cycle. exceptions are the timer 2 baud rate and clock- o ut modes in which the timer register is incremented by the system clock divided by two. for counter operation (c/tx#= 1), the timer register counts the negative transitions on the tx external input pin. the external input is sampled during every s5p2 state. the programmer ? s guide describes the notation for the states in a peripheral cycle. when the sample is high in one cycle and low in the next one, the counter is incremented. the new count value appears in the register during the next s3p1 state after the transition has been detected. since it takes 12 states (24 oscillator periods) to recognize a nega- tive transition, the maximum count rate is 1/24 of the oscillator frequency. there are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full periph- eral cycle. timer 0 timer 0 functions as either a timer or an event counter in four operating modes. figure 71 through figure 77 show the logic configuration of each mode. timer 0 is controlled by the four lower bits of the tmod register (see table 83 on page 115) and bits 0, 1, 4 and 5 of the tcon register (see table 82 on page 114). the tmod register selects the method of timer gating (gate0), timer or counter operation (t/c0#) and the operating mode (m10 and m00). the tcon register provides timer 0 control functions: overflow flag (tf0), run control bit (tr0), interrupt flag (ie0) and inter- rupt type control bit (it0).
110 at8xc5122/23 4202b ? scr ? 07/03 for normal timer operation (gate0= 0), setting tr0 allows tl0 to be incremented by the selected input. setting gate0 and tr0 allows external pin int0# to control timer operation. timer 0 overflow (count rolls over from all 1s to all 0s) sets the tf0 flag and generates an interrupt request. it is important to stop the timer/counter before changing modes. mode 0 (13-bit timer) mode 0 configures timer 0 as a 13-bit timer which is set up as an 8-bit timer (th0 reg- ister) with a modulo-32 prescaler implemented with the lower five bits of the tl0 register (see figure 71). the upper three bits of the tl0 register are indeterminate and should be ignored. prescaler overflow increments the th0 register. figure 72 gives the overflow period calculation formula. figure 71. timer/counter x (x= 0 or 1) in mode 0 figure 72. mode 0 overflow period formula mode 1 (16-bit timer) mode 1 configures timer 0 as a 16-bit timer with the th0 and tl0 registers connected in a cascade (see figure 73). the selected input increments the tl0 register. figure 74 gives the overflow period calculation formula when in timer mode. trx tcon reg tfx tcon reg 0 1 gatex tmod reg overflow timer x interrupt request c/tx# tmod reg tlx (5 bits) thx (8 bits) intx# tx fck_tx /6 6 ? (16384 ? (thx, tlx)) tfx per = f ck_tx
111 at8xc5122/23 4202b ? scr ? 07/03 figure 73. timer/counter x (x = 0 or 1) in mode 1 figure 74. mode 1 overflow period formula mode 2 (8-bit timer with auto- reload) mode 2 configures timer 0 as an 8-bit timer (tl0 register) that automatically reloads from the th0 register (see figure 75). tl0 overflow sets the tf0 flag in the tcon reg- ister and reloads tl0 with the contents of th0, which is preset by the software. when the interrupt request is serviced, the hardware clears tf0. the reload leaves th0 unchanged. the next reload value may be changed at any time by writing it to the th0 register. figure 76 gives the autoreload period calculation formula when in timer mode. figure 75. timer/counter x (x = 0 or 1) in mode 2 figure 76. mode 2 autoreload period formula trx tcon reg tfx tcon reg 0 1 gatex tmod reg overflow timer x interrupt request c/tx# tmod reg tlx (8 bits) thx (8 bits) intx# tx fck_tx /6 6 ? (65536 ? (thx, tlx)) tfx per = f ck_tx trx tcon reg tfx tcon reg 0 1 gatex tmod reg overflow timer x interrupt request c/tx# tmod reg tlx (8 bits) thx (8 bits) intx# tx fck_tx /6 tfx per = f ck_tx 6 ? (256 ? thx)
112 at8xc5122/23 4202b ? scr ? 07/03 mode 3 (two 8-bit timers) mode 3 configures timer 0 so that registers tl0 and th0 operate as 8-bit timers (see figure 77). this mode is provided for applications requiring an additional 8-bit timer or counter. tl0 uses the timer 0 control bits c/t0# and gate0 in the tmod register, and tr0 and tf0 in the tcon register in the normal manner. th0 is locked into a timer function (counting f uart ) and takes over use of the timer 1 interrupt (tf1) and run con- trol (tr1) bits. thus, operation of timer 1 is restricted when timer 0 is in mode 3. figure 78 gives the autoreload period calculation formulas for both tf0 and tf1 flags. figure 77. timer/counter 0 in mode 3: two 8-bit counters figure 78. mode 3 overflow period formula timer 1 timer 1 is identical to timer 0 except for mode 3 which is a hold-count mode. the fol- lowing comments help to understand the differences: timer 1 functions as either a timer or an event counter in three operating modes. figure 71 through figure 75 show the logical configuration for modes 0, 1, and 2. mode 3 of timer 1 is a hold-count mode. timer 1 is controlled by the four high-order bits of the tmod register (see table 83 on page 115) and bits 2, 3, 6 and 7 of the tcon register (see table 82 on page 114). the tmod register selects the method of timer gating (gate1), timer or counter operation (c/t1#) and the operating mode (m11 and m01). the tcon register provides timer 1 control functions: overflow flag (tf1), run control bit (tr1), interrupt flag (ie1) and the interrupt type control bit (it1). timer 1 can serve as the baud rate generator for the serial port. mode 2 is best suited for this purpose. for normal timer operation (gate1 = 0), setting tr1 allows tl1 to be incremented by the selected input. setting gate1 and tr1 allows external pin int1# to control timer operation. timer 1 overflow (count rolls over from all 1s to all 0s) sets the tf1 flag and generates an interrupt request. tr0 tcon.4 tf0 tcon.5 int0# 0 1 gate0 tmod.3 overflow timer 0 interrupt request c/t0# tmod.2 tl0 (8 bits) tr1 tcon.6 th0 (8 bits) tf1 tcon.7 overflow timer 1 interrupt request t0 fck_t0 /6 fck_t0 /6 tf0 per = f ck_t0 6 ? (256 ? tl0) tf1 per = f ck_t0 6 ? (256 ? th0)
113 at8xc5122/23 4202b ? scr ? 07/03 when timer 0 is in mode 3, it uses timer 1 ? s overflow flag (tf1) and run control bit (tr1). for this situation, use timer 1 only for applications that do not require an interrupt (such as a baud rate generator for the serial port) and switch timer 1 in and out of mode 3 to turn it off and on. it is important to stop the timer/counter before changing modes. mode 0 (13-bit timer) mode 0 configures timer 1 as a 13-bit timer, which is set up as an 8-bit timer (th1 reg- ister) with a modulo-32 prescaler implemented with the lower 5 bits of the tl1 register (see figure 71). the upper 3 bits of tl1 register are ignored. prescaler overflow incre- ments the th1 register. mode 1 (16-bit timer) mode 1 configures timer 1 as a 16-bit timer with th1 and tl1 registers connected in cascade (see figure 73). the selected input increments the tl1 register. mode 2 (8-bit timer with auto- reload) mode 2 configures timer 1 as an 8-bit timer (tl1 register) with automatic reload from the th1 register on overflow (see figure 75). tl1 overflow sets the tf1 flag in the tcon register and reloads tl1 with the contents of th1, which is preset by the soft- ware. the reload leaves th1 unchanged. mode 3 (halt) placing timer 1 in mode 3 causes it to halt and hold its count. this can be used to halt timer 1 when the tr1 run control bit is not available i.e. when timer 0 is in mode 3.
114 at8xc5122/23 4202b ? scr ? 07/03 registers timer/counter control register reset value = 0000 0000b table 82. tcon (s:88h) 76543210 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 bit number bit mnemonic description 7tf1 timer 1 overflow flag cleared by the hardware when processor vectors interrupt routine. set by the hardware on timer/counter overflow when timer 1 register overflows. 6tr1 timer 1 run control bit clear to turn off timer/counter 1. set to turn on timer/counter 1. 5tf0 timer 0 overflow flag cleared by the hardware when processor vectors interrupt routine. set by the hardware on timer/counter overflow when timer 0 register overflows. 4tr0 timer 0 run control bit clear to turn off timer/counter 0. set to turn on timer/counter 0. 3ie1 interrupt 1 edge flag cleared by the hardware when interrupt is processed if edge-triggered (see it1). set by the hardware when external interrupt is detected on the int1# pin. 2it1 interrupt 1 type control bit clear to select low level active (level triggered) for external interrupt 1 (int1#). set to select falling edge active (edge triggered) for external interrupt 1. 1ie0 interrupt 0 edge flag cleared by the hardware when interrupt is processed if edge-triggered (see it0). set by the hardware when external interrupt is detected on int0# pin. 0it0 interrupt 0 type control bit clear to select low level active (level triggered) for external interrupt 0 (int0#). set to select falling edge active (edge triggered) for external interrupt 0.
115 at8xc5122/23 4202b ? scr ? 07/03 reset value = 0000 0000b table 83. timer/counter mode control register - tmod (s:89h) 76543210 gate1 c/t1# m11 m01 gate0 c/t0# m10 m00 bit number bit mnemonic description 7gate1 timer 1 gating control bit clear to enable timer 1 whenever tr1 bit is set. set to enable timer 1 only while int1# pin is high and tr1 bit is set. 6c/t1# timer 1 counter/timer select bit clear for timer operation: timer 1 counts the divided-down system clock. set for counter operation: timer 1 counts negative transitions on external pin t1. 5m11 timer 1 mode select bits m11 m01 operating mode 0 0 mode 0:8-bit timer/counter (th1) with 5-bit prescaler (tl1). 0 1 mode 1:16-bit timer/counter. 1 0 mode 2:8-bit auto-reload timer/counter (tl1). reloaded from th1 at overflow. 1 1 mode 3:timer 1 halted. retains count. 4m01 3gate0 timer 0 gating control bit clear to enable timer 0 whenever tr0 bit is set. set to enable timer/counter 0 only while int0# pin is high and tr0 bit is set. 2c/t0# timer 0 counter/timer select bit clear for timer operation: timer 0 counts the divided-down system clock. set for counter operation: timer 0 counts negative transitions on external pin t0. 1m10 timer 0 mode select bit m10 m00 operating mode 0 0 mode 0:8-bit timer/counter (th0) with 5-bit prescaler (tl0). 0 1 mode 1:16-bit timer/counter. 1 0 mode 2:8-bit auto-reload timer/counter (tl0). reloaded from th0 at overflow. 1 1 mode 3:tl0 is an 8-bit timer/counter. th0 is an 8-bit timer using timer 1 ? s tr0 and tf0 bits. 0m00
116 at8xc5122/23 4202b ? scr ? 07/03 reset value = 0000 0000b reset value = 0000 0000b reset value = 0000 0000b reset value = 0000 0000b table 84. timer 0 high byte register - th0 (s:8ch) 76543210 bit number bit mnemonic description 7:0 high byte of timer 0 table 85. timer 0 low byte register - tl0 (s:8ah) 76543210 bit number bit mnemonic description 7:0 low byte of timer 0 table 86. timer 1 high byte register - th1 (s:8dh) 76543210 bit number bit mnemonic description 7:0 high byte of timer 1 table 87. timer 1 low byte register - tl1 (s:8bh) 76543210 bit number bit mnemonic description 7:0 low byte of timer 1
117 at8xc5122/23 4202b ? scr ? 07/03 keyboard interface only for at8xc5122. introduction the at8xc5122/23 implements a keyboard interface allowing the connection of a 8 x n matrix keyboard. it is based on 8 inputs with programmable interrupt capability on both high or low level. these inputs are available as alternate function of p5 and allow to exit from idle and power-down modes. description the keyboard interfaces with the c51 core through 3 special function registers: kbls, the keyboard level selection register (table 90 on page 120), kbe, the keyboard interrupt enable register (table 89 on page 119), and kbf, the keyboard flag register (table ). interrupt the keyboard inputs are considered as 8 independent interrupt sources sharing the same interrupt vector. an interrupt enable bit ( kbd in ie1) allows global enable or dis- able of the keyboard interrupt (see figure 79). as detailed in figure 80 each keyboard input has the capability to detect a programmable level according to kbls.x bit value. level detection is then reported in interrupt flags kbf.x that can be masked by software using kbe.x bits. this structure allows keyboard arrangement from 1 by n to 8 by n matrix and allows usage of p5 inputs for other purpose. the kbf.x flags are set by hardware when an active level is on input p5.x. they are automatically reset after any read access on kbf. if the content of kbf must be ana- lyzed, the first read instruction must transfer kbf contend to another location. the kbf register cannot be written by software. figure 79. keyboard interface block diagram figure 80. keyboard input circuitry p5.0 keyboard interface interrupt request ekb ien1.0 input circuitry p5.1 input circuitry p5.2 input circuitry p5.3 input circuitry p5.4 input circuitry p5.5 input circuitry p5.6 input circuitry p5.7 input circuitry kbdit p5.x kbe.x kbf.x kbls.x 0 1
118 at8xc5122/23 4202b ? scr ? 07/03 power reduction mode p5 inputs allow exit from idle and power-down modes as detailed in section "power- down mode". registers reset value = 0000 0000b table 88. keyboard flag register - kbf (9eh) 76543210 kbf7 kbf6 kbf5 kbf4 kbf3 kbf2 kbf1 kbf0 bit number bit mnemonic description 7kbf7 keyboard line 7 flag set by hardware when the port line 7 detects a programmed level. it generates a keyboard interrupt request if the kbkbie.7 bit in kbie register is set. cleared by hardware after the read of the kbf register. 6kbf6 keyboard line 6 flag set by hardware when the port line 6 detects a programmed level. it generates a keyboard interrupt request if the kbie.6 bit in kbie register is set. cleared by hardware after the read of the kbf register. 5kbf5 keyboard line 5 flag set by hardware when the port line 5 detects a programmed level. it generates a keyboard interrupt request if the kbie.5 bit in kbie register is set. cleared by hardware after the read of the kbf register. 4kbf4 keyboard line 4 flag set by hardware when the port line 4 detects a programmed level. it generates a keyboard interrupt request if the kbie.4 bit in kbie register is set. cleared by hardware after the read of the kbf register. 3kbf3 keyboard line 3 flag set by hardware when the port line 3 detects a programmed level. it generates a keyboard interrupt request if the kbie.3 bit in kbie register is set. cleared by hardware after the read of the kbf register. 2kbf2 keyboard line 2 flag set by hardware when the port line 2 detects a programmed level. it generates a keyboard interrupt request if the kbie.2 bit in kbie register is set. cleared by hardware after the read of the kbf register. 1kbf1 keyboard line 1 flag set by hardware when the port line 1 detects a programmed level. it generates a keyboard interrupt request if the kbie.1 bit in kbie register is set. cleared by hardware after the read of the kbf register. 0kbf0 keyboard line 0 flag set by hardware when the port line 0 detects a programmed level. it generates a keyboard interrupt request if the kbie.0 bit in kbie register is set. cleared by hardware after the read of the kbf register.
119 at8xc5122/23 4202b ? scr ? 07/03 reset value = 0000 0000b table 89. keyboard input enable register - kbe (9dh) 76543210 kbe7 kbe6 kbe5 kbe4 kbe3 kbe2 kbe1 kbe0 bit number bit mnemonic description 7 kbe7 keyboard line 7 enable bit cleared to enable standard i/o pin. set to enable kbf.7 bit in kbf register to generate an interrupt request. 6 kbe6 keyboard line 6 enable bit cleared to enable standard i/o pin. set to enable kbf.6 bit in kbf register to generate an interrupt request. 5 kbe5 keyboard line 5 enable bit cleared to enable standard i/o pin. set to enable kbf.5 bit in kbf register to generate an interrupt request. 4 kbe4 keyboard line 4 enable bit cleared to enable standard i/o pin. set to enable kbf.4 bit in kbf register to generate an interrupt request. 3 kbe3 keyboard line 3 enable bit cleared to enable standard i/o pin. set to enable kbf.3 bit in kbf register to generate an interrupt request. 2 kbe2 keyboard line 2 enable bit cleared to enable standard i/o pin. set to enable kbf.2 bit in kbf register to generate an interrupt request. 1 kbe1 keyboard line 1 enable bit cleared to enable standard i/o pin. set to enable kbf.1 bit in kbf register to generate an interrupt request. 0 kbe0 keyboard line 0 enable bit cleared to enable standard i/o pin. set to enable kbf.0 bit in kbf register to generate an interrupt request.
120 at8xc5122/23 4202b ? scr ? 07/03 reset value = 0000 0000b table 90. keyboard level selector register - kbls (9ch) 76543210 kbls7 kbls6 kbls5 kbls4 kbls3 kbls2 kbls1 kbls0 bit number bit mnemonic description 7kbls7 keyboard line 7 level selection bit cleared to enable a low level detection on port line 7. set to enable a high level detection on port line 7. 6kbls6 keyboard line 6 level selection bit cleared to enable a low level detection on port line 6. set to enable a high level detection on port line 6. 5kbls5 keyboard line 5 level selection bit cleared to enable a low level detection on port line 5. set to enable a high level detection on port line 5. 4kbls4 keyboard line 4 level selection bit cleared to enable a low level detection on port line 4. set to enable a high level detection on port line 4. 3kbls3 keyboard line 3 level selection bit cleared to enable a low level detection on port line 3. set to enable a high level detection on port line 3. 2kbls2 keyboard line 2 level selection bit cleared to enable a low level detection on port line 2. set to enable a high level detection on port line 2. 1kbls1 keyboard line 1 level selection bit cleared to enable a low level detection on port line 1. set to enable a high level detection on port line 1. 0kbls0 keyboard line 0 level selection bit cleared to enable a low level detection on port line 0. set to enable a high level detection on port line 0.
121 at8xc5122/23 4202b ? scr ? 07/03 interrupt system the at8xc5122/23 implements an interrupt controller with 15 inputs but only 9 are used: two external interrupts (int0 and int1 ), two timer interrupts (timers 0, 1), the serial port interrupt, spi interrupt, keyboard interrupt, usb interrupt and the scib global interrupt.
122 at8xc5122/23 4202b ? scr ? 07/03 figure 81. interrupt control system each of the interrupt sources can be individually enabled or disabled by setting or clear- ing a bit in the interrupt enable registers (table 92 on page 125 and table 93 on page 126). these registers also contain a global disable bit, which must be cleared to disable all interrupts at once. ie0 spi smart card int1/oe cpres rxd rxen 0 1 ie1 1 0 0 1 presit isel.0 isel.4 rxit oeen isel.2 oelev isel.3 it1 tcon.2 tcon.3 presen isel.1 cplev isel.7 isel.5 0 1 it0 tcon.0 tf0 tf1 ri ti et1 ien0.3 eusb ien1.6 es ien0.4 ex0 ien0.0 00 01 10 11 ea ien0.7 et0 ien0.1 ex1 ien0.2 ekb (1) ien1.0 espi (1) ien1.2 iph/l interrupt enable lowest priority priority enable 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 esci ien1.3 00 01 10 11 highest priority interrupts interrupts tcon.1 int0# rxd txd d+ d- cio cclk mosi sck miso tcon.5 tcon.7 scon.0 scon.1 p5.x 0 1 kbfx kbex kblsx serial interface controller controller usb controller controller interface note (1): only for at8xc5122 (1)
123 at8xc5122/23 4202b ? scr ? 07/03 each interrupt source can also be individually programmed to one out of four priority lev- els by setting or clearing a bit in the interrupt priority low registers (table 95 on page 127 and table 97 on page 129) and in the interrupt priority high register (table 96 on page 128 and table 99 on page 131) shows the bit values and priority levels associated with each combination. int1 interrupt vector the int1 interrupt is multiplexed with the following three inputs: int1/oe : standard 8051 interrupt input rxd: received data on uart cpres: insertion or remove of the main card the setting configurations for each input is detailed below. int1 /oe input this interrupt input is active under the following conditions : it must be enabled by oeen bit (isel register) it can be active on a level or falling edge following it1 bit (tcon register) status if level triggering selection is set, the active level 0 or 1 can be selected with oelev bit (isel register) the bit ie1 (tcon register) is set by hardware when external interrupt detected. it is cleared when interrupt is processed. rxd input a second vector interrupt input is the reception of a character. uart rx input can gen- erate an interrupt if enabled with bit rxen (isel.0). the global enable bits ex1 and ea must also be set. then, the bit rxit (isel register) is set by hardware when a low level is detected on p3.0/rxd input. cpres input the third input is the detection of a level change on cpres input (p1.2). this input can generate an interrupt if enabled with presen (isel.1) , ex1 (ie0.2) and ea (ie0.7) bits. this detection is done according to the level selected with bit cplev (isel.7). then the bit presit (isel.5) is set by hardware when the triggering conditions are met. this bit must be cleared by software. registers a low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. a high-priority interrupt can ? t be interrupted by any other interrupt source. if two interrupt requests of different priority levels are received simultaneously, the request of higher priority level is serviced. if interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced first. thus within each priority level there is a second priority structure deter- mined by the polling sequence.
124 at8xc5122/23 4202b ? scr ? 07/03 table 91. priority level bit values iph.x ipl.x interrupt level priority 0 0 0 (lowest) 011 102 1 1 3 (highest)
125 at8xc5122/23 4202b ? scr ? 07/03 reset value = 0000 0000b (bit addressable) table 92. interrupt enable register 0 - ien0 (a8h) 76543210 ea - - es et1 ex1 et0 ex0 bit number bit mnemonic description 7ea enable all interrupt bit cleared to disable all interrupts. set to enable all interrupts. 6 - 5 - reserved the value read from this bit is indeterminate. do not change these bits. 4es serial port enable bit cleared to disable serial port interrupt. set to enable serial port interrupt. 3et1 timer 1 overflow interrupt enable bit cleared to disable timer 1 overflow interrupt. set to enable timer 1 overflow interrupt. 2ex1 external interrupt 1 enable bit cleared to disable external interrupt 1. set to enable external interrupt 1. 1et0 timer 0 overflow interrupt enable bit cleared to disable timer 0 overflow interrupt. set to enable timer 0 overflow interrupt. 0ex0 external interrupt 0 enable bit cleared to disable external interrupt 0. set to enable external interrupt 0.
126 at8xc5122/23 4202b ? scr ? 07/03 reset value = x0xx 00x0b (bit addressable) table 93. interrupt enable register 1 - ien1 (b1h) for at8xc5122 76543210 - eusb - - esci espi - ekb bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not change this bit. 6eusb usb interrupt enable bit cleared to disable usb interrupt . set to enable usb interrupt. 5 - 4 - reserved the value read from this bit is indeterminate. do not change these bits. 3esci sci interrupt enable bit cleared to disable sciinterrupt . set to enable sci interrupt. 2 espi spi interrupt enable bit cleared to disable spi interrupt . set to enable spi interrupt. 1- reserved the value read from this bit is indeterminate. do not change this bit. 0ekb keyboard interrupt enable bit cleared to disable keyboard interrupt . set to enable keyboard interrupt.
127 at8xc5122/23 4202b ? scr ? 07/03 reset value = x0xx 0xxxb (bit addressable) reset value = x000 0000b (bit addressable) table 94. interrupt enable register 1 - ien1 (b1h) for at8xc5123 76543210 -eusb- - esci - bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not change this bit. 6eusb usb interrupt enable bit cleared to disable usb interrupt . set to enable usb interrupt. 5 - 4 - reserved the value read from this bit is indeterminate. do not change these bits. 3esci sci interrupt enable bit cleared to disable sciinterrupt . set to enable sci interrupt. 2 reserved the value read from this bit is indeterminate. do not change this bit. 1- reserved the value read from this bit is indeterminate. do not change this bit. 0 reserved the value read from this bit is indeterminate. do not change this bit. table 95. interrupt priority low register 0 - ipl0 (b8h) 76543210 - - - psl pt1lpx1lpt0lpx0l bit number bit mnemonic description 7 - 5 - reserved the value read from this bit is indeterminate. do not change these bits. 4psl serial port priority bit refer to psh for priority level. 3pt1l timer 1 overflow interrupt priority bit refer to pt1h for priority level. 2 px1l external interrupt 1 priority bit refer to px1h for priority level. 1pt0l timer 0 overflow interrupt priority bit refer to pt0h for priority level. 0 px0l external interrupt 0 priority bit refer to px0h for priority level.
128 at8xc5122/23 4202b ? scr ? 07/03 reset value = x000 0000b (not bit addressable) table 96. interrupt priority high register 0 - iph0 (b7h) 76543210 - - - psh pt1h px1h pt0h px0h bit number bit mnemonic description 7 - 5 - reserved the value read from this bit is indeterminate. do not change these bits. 4psh serial port priority high bit psh psl priority level 0 0 lowest 01 10 1 1 highest 3pt1h timer 1 overflow interrupt priority high bit pt1h pt1l priority level 0 0 lowest 01 10 1 1 highest 2px1h external interrupt 1 priority high bit px1h px1l priority level 0 0 lowest 01 10 1 1 highest 1pt0h timer 0 overflow interrupt priority high bit pt0h pt0l priority level 0 0 lowest 01 10 1 1 highest 0px0h external interrupt 0 priority high bit px0h px0l priority level 0 0 lowest 01 10 1 1 highest
129 at8xc5122/23 4202b ? scr ? 07/03 reset value = x00x 00x0b (bit addressable) table 97. interrupt priority low register 1 - ipl1 (b2h) for at8xc5122 76543210 - pusbl - - pscil pspil - pkbdl bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not change this bit. 6pusbl usb interrupt priority bit refer to pusbh for priority level. 5 - 4 - reserved the value read from this bit is indeterminate. do not change these bits. 3pscil sci interrupt priority bit refer to pspih for priority level. 2 pspil spi interrupt priority bit refer to pspih for priority level. 1- reserved the value read from this bit is indeterminate. do not change this bit. 0pkbl keyboard interrupt priority bit refer to pkbdh for priority level.
130 at8xc5122/23 4202b ? scr ? 07/03 reset value = x0xx 0xxxb (bit addressable) table 98. interrupt priority low register 1 - ipl1 (b2h) for at8xc5123 76543210 - pusbl - - pscil bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not change this bit. 6pusbl usb interrupt priority bit refer to pusbh for priority level. 5 - 4 - reserved the value read from this bit is indeterminate. do not change these bits. 3pscil sci interrupt priority bit refer to pspih for priority level. 2 reserved the value read from this bit is indeterminate. do not change this bit. 1 reserved the value read from this bit is indeterminate. do not change this bit. 0 reserved the value read from this bit is indeterminate. do not change this bit.
131 at8xc5122/23 4202b ? scr ? 07/03 reset value = xxxx x000b (not bit addressable) table 99. interrupt priority high register 1 - iph1 (b3h) for at8xc5122 76543210 - pusbh - - pscih - b it number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not change this bit. 6pusbh usb interrupt priotity high bit pusbh pusbl priority level 0 0 lowest 01 10 1 1 highest 5-4 - reserved the value read from this bit is indeterminate. do not change these bits. 3pscih sci interrupt priority high bit pscih pscil priority level 0 0 lowest 01 10 1 1 highest 2pspih spi interrupt priority high bit pspih pspil priority level 0 0 lowest 01 10 1 1 highest 1- reserved the value read from this bit is indeterminate. do not change this bit. 0pkbh keyboard interrupt priority high bit pkbdh pkbdl priority level 0 0 lowest 01 10 1 1 highest
132 at8xc5122/23 4202b ? scr ? 07/03 reset value = x0xx 0xxxb (not bit addressable) table 100. interrupt priority high register 1 - iph1 (b3h) for at8xc5123 76543210 -pusbh--pscih--- b it number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not change this bit. 6pusbh usb interrupt priotity high bit pusbh pusbl priority level 0 0 lowest 01 10 1 1 highest 5-4 - reserved the value read from this bit is indeterminate. do not change these bits. 3pscih sci interrupt priority high bit pscih pscil priority level 0 0 lowest 01 10 1 1 highest 2 reserved the value read from this bit is indeterminate. do not change these bits. 1- reserved the value read from this bit is indeterminate. do not change this bit. 0 reserved the value read from this bit is indeterminate. do not change these bits.
133 at8xc5122/23 4202b ? scr ? 07/03 reset value = 0000 0000b table 101. interrupt enable register - isel (s:a1h) 76543210 cplev - presit rxit oelev oeen presen rxen bit number bit mnemonic description 7 cplev card presence detection level this bit indicates which cpres level will bring about an interrupt set this bit to indicate that card presence it will appear if cpres is at high level. clear this bit to indicate that card presence it will appear if cpres is at low level. 6- reserved the value read from this bit is indeterminate. do not change this bit. 5 presit card presence detection interrupt flag set by hardware must be cleared by software 4 rxit received data interrupt flag set by hardware must be cleared by software 3 oelev oe/int1 signal active level set this bit to indicate that high level is active. clear this bit to indicate that low level is active. 2 oeen oe/int1 interrupt disable bit clear to disable int1 interrupt set to enable int1 interrupt 1 presen card presence detection interrupt enable bit clear to disable the card presence detection interrupt coming from scib. set to enable the card presence detection interrupt coming from scib. 0 rxen received data interrupt enable bit clear to disable the rxd interrupt. set to enable the rxd interrupt (a minimal bit width of 100 s is required to wake up from power-down) .
134 at8xc5122/23 4202b ? scr ? 07/03 interrupt sources and vector addresses note: 1. only fot at8xc5122 table 102. interrupt vectors interrupt source polling priority at same level vector address reset 0 (highest priority) c:0000h int0 1 c:0003h timer 0 2 c:000bh int1 3 c:0013h timer 1 4 c:001bh uart 6 c:0023h reserved 7 c:002bh reserved 5 c:0033h keyboard controller (1) 8 c:003bh reserved 9 c:0043h spi controller (1) 10 c:004bh smart card controller 11 c:0053h reserved 12 c:005bh reserved 13 c:0063h usb controller 14 c:006bh reserved 15 (lowest priority) c:0073h
135 at8xc5122/23 4202b ? scr ? 07/03 reset and power monitor reset from the system point of view, the reset controller must provide the following four functions: an active reset each time the reset pin is set to a low state. an active reset during power on sequence without the need of external components a device protection for preventing code execution if the power supply goes out of the functional range of the microcontroller ? s core. a watchdog function therefore the reset controller is fed by three sources: - signal coming from reset pin - signal coming from power monitor circuit assuring the power on reset and the power fail detect functions - watchdog circuit
136 at8xc5122/23 4202b ? scr ? 07/03 figure 82. reset controller regulator 3.3v vss dvcc rst c51 core vcc vpfdm vpfdp dvcc vpfd 0 1 vpfd vcc xtal2 xtal1 osc. watchdog output internal reset 0 1 1024 counter time q time 1024*tclkout vpfd clkin q vcc/2-0.5 vcc/2+0.5 clkin clkout 0 1 power monitor analog buffer clkout
137 at8xc5122/23 4202b ? scr ? 07/03 power monitor overview the power monitor function supervises the evolutions of the voltages feeding the micro- controller, and if needed, suspends its activity when the detected value is out of specification. it guarantees to start up properly when at8xc5122 is powered up and prevents code execution errors when the regulated power supply becomes lower than the functional threshold. this section describes the functions of the power monitor. description in order to startup and to maintain properly the microcontroller operation, vcc has to be stabilized in the vcc operating range and the oscillator has to be stabilised with a nom- inal amplitude compatible with logic threshold. this control is carried out during three phases which are the power-up, normal operation and stop. so it is in accordance with the following requirements: it guarantees an operationnal reset when the microcontroller is powered and a protection if the power supply goes out from the functional range of the microcontroller. figure 83. power monitor block diagram power monitor diagram the target of the power monitor is to survey the power-supply in order to detect any volt- age drops which are not in the target specification. this power monitor checks two kind of situations which occur: during the power-up condition, when vcc is reaching the product specification, during a steady-state condition, when vcc is stable but disturbed by any undesirable voltage drops. figure 84 shows some configurations which can be met by the power monitor. external power-supply dc to dc 3.3v regulator vcc dvcc cvcc internal reset power fail detector power up detector
138 at8xc5122/23 4202b ? scr ? 07/03 figure 84. power-up and steady-state conditions monitored such device when it is integrated in a microcontroller, forces the cpu in reset mode when vcc reaches a voltage condition which is out of the specification. the thresholds and their functions are: vpfdp: the output voltage of the regulator has reached a minimum functional value at the power-up. the circuit leaves the reset mode. vpfdm: the output voltage of the regulator has reached a low threshold functional value for the microcontroller. an internal reset is set. a glitch filtering prevents the system to reset when short duration glitches are carried on dvcc power-supply. power-up steady state condition dvcc t reset vpfdp vpfdm t g vcc
139 at8xc5122/23 4202b ? scr ? 07/03 watchdog timer at8xc5122 contains a powerfull programmable hardware watchdog timer (wdt) that automatically resets the chip if its software fails to reset the wdt before the selected time interval has elapsed. it permits large timeout ranking from 16 ms to 2s @fosc = 12 mhz. this wdt consist of a 14-bit counter plus a 7 - bit programmable counter, a watchdog timer reset register (wdtrst) and a watchdog timer programmation (wdtprg) reg- ister. when exiting reset, the wdt is -by default- disable. to enable the wdt, the user has to write the sequence 1eh and e1h into wdrst register. when the watchdog timer is enabled, it will increment every machine cycle while the oscillator is running and there is no way to disable the wdt except through reset (either hardware reset or wdt overflow reset). when wdt overflows, it will generate an output reset pulse at the rst pin. the reset pulse duration is 96xt osc , where t osc =1/f osc . to make the best use of the wdt, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a wdt reset. the wdt is controlled by two registers (wdtrst and wdtprg). figure 85. watchdog timer reset decoder control wdtrst wr enable 14-bit counter 7 - bit counter outputs f ck_wd reset - - - - - 2 1 0 wdtprg
140 at8xc5122/23 4202b ? scr ? 07/03 reset value = xxxx x000b the three lower bits (s0, s1, s2) located into wdtprg register enables to program the wdt duration. to compute wd timeout, the following formula is applied: time out = 6 * (2 14 * 2 svalue - 1 ) / f ck_wd note: svalue represents the decimal value of (s2 s1 s0) / ckrl represents the prescaler table 103. watchdog timer out register - wdtprg (0a7h) 76543210 -----s2s1s0 bit number bit mnemonic description 7 - 3 - reserved the value read from this bit is indeterminate. do not change these bits. 2 s2 wdt time-out select bit 2 1 s1 wdt time-out select bit 1 0 s0 wdt time-out select bit 0 table 104. machine cycle count s2 s1 s0 machine cycle count 000 2 14 - 1 001 2 15 - 1 010 2 16 - 1 011 2 17 - 1 100 2 18 - 1 101 2 19 - 1 110 2 20 - 1 111 2 21 - 1
141 at8xc5122/23 4202b ? scr ? 07/03 table 105. timeout value for fosc = 12 mhz reset value = xxxx xxxxb the wdtrst register is used to reset/enable the wdt by writing 1eh then e1h in sequence. watchdog timer during power-down mode and idle in power-down mode the oscillator stops, which means the wdt also stops. while in power-down mode the user does not need to service the wdt. there are 2 methods of exiting power-down mode: by a hardware reset or via a level activated external interrupt which is enabled prior to entering power-down mode. when power-down is exited with hardware reset, servicing the wdt should occur as it normally does whenever at8xc5122 is reset. exiting power-down with an interrupt is significantly different. the interrupt is held low long enough for the oscillator to stabilize. when the interrupt is brought high, the interrupt is serviced. to prevent the wdt from resetting the device while the interrupt pin is held low, the wdt is not started until the interrupt is pulled high. it is suggested that the wdt be reset during the interrupt service for the interrupt used to exit power-down. to ensure that the wdt does not overflow within a few states of exiting of powerdown, it is best to reset the wdt just before entering powerdown. in the idle mode, the oscillator continues to run. to prevent the wdt from resetting while in idle mode, the user should always set up a timer that will periodically exit idle, service the wdt, and re-enter idle mode. s2 s1 s0 timeout for f ck_wd = 6 mhz 0 0 0 16.38 ms 0 0 1 32.77 ms 0 1 0 65.54 ms 0 1 1 131.07 ms 1 0 0 262.14 ms 1 0 1 524.29 ms 1 1 0 1.05 s 1 1 1 2.10 s table 106. watchdog timer enable register (write only) - wdtrst (a6h) 76543210 --------
142 at8xc5122/23 4202b ? scr ? 07/03 power management idle mode an instruction that sets pcon.0 indicates that it is the last instruction to be executed before going into the idle mode. in the idle mode, the internal clock signal is gated off to the cpu, but not to the interrupt, timer, and serial port functions. the cpu status is preserved in its entirety: the stack pointer, program counter, program status word, accumulator and all other registers maintain their data during idle. the port pins hold the logical states they had at the time idle was activated. ale and psen hold at logic high level. there are two ways to terminate the idle mode. activation of any enabled interrupt will cause pcon.0 to be cleared by hardware, terminating the idle mode. the interrupt will be serviced, and following reti the next instruction to be executed will be the one fol- lowing the instruction that put the device into idle. the flag bits gf0 and gf1 can be used to give an indication if an interrupt occured dur- ing normal operation or during an idle. for example, an instruction that activates idle can also set one or both flag bits. when idle is terminated by an interrupt, the interrupt service routine can examine the flag bits. the other way of terminating the idle mode is with a hardware reset. since the clock oscillator is still running, the hardware reset needs to be held active for only two machine cycles (24 oscillator periods) to complete the reset. power-down mode to save maximum power, a power-down mode can be invoked by software (see table 13, pcon register). warning: to minimize power consumption, all peripherals and i/os with static current consumption must be set in the proper state. i/os programmed with low speed output configuration (kb_out) must be switch to push-pull or standard c51 configuration before entering power-down. the cvcc generator must also be switch off. in power-down mode, the oscillator is stopped and the instruction that invoked power- down mode is the last instruction executed. the internal ram and sfrs retain their value until the power-down mode is terminated. v cc can be lowered to save further power. either a hardware reset or an external interrupt can cause an exit from power- down. to properly terminate power-down, the reset or external interrupt should not be executed before v cc is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize. only external interrupts int0 , int1 , keyboard, card insertion/removal and usb inter- rupts are useful to exit from power-down. for that, interrupt must be enabled and configured as level or edge sensitive interrupt input. when keyboard interrupt occurs after a power-down mode, 1024 clocks are necessary to exit to power-down mode and enter in operating mode. holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed in figure 86. when both interrupts are enabled, the oscillator restarts as soon as one of the two inputs is held low and power-down exit will be completed when the first input is released. in this case, the higher priority interrupt service routine is executed. once the interrupt is serviced, the next instruction to be executed after reti will be the one following the instruction that put at8xc5122/23 into power-down mode.
143 at8xc5122/23 4202b ? scr ? 07/03 figure 86. power-down exit waveform exit from power-down by reset redefines all the sfrs, exit from power-down by external interrupt does no affect the sfrs. exit from power-down by either reset or external interrupt does not affect the internal ram content. note: if idle mode is activated with power-down mode (idl and pd bits set), the exit sequence is unchanged, when execution is vectored to interrupt, pd and idl bits are cleared and idle mode is not entered. table 107 shows the state of ports during idle and power-down modes. note: 1. port 0 can force a 0 level. a "one" will leave port floating. reduced emi mode the ale signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. nevertheless, during internal code execution, ale signal is still generated. in order to reduce emi, ale signal can be disabled by setting ao bit. the ao bit is located in auxr register at bit location 0. as soon as ao is set, ale is no longer output but remains active during movx and movc instructions and external fetches. during ale disabling, ale pin is weakly pulled high. int1 int0 xtal1 power-down phase oscillator restart phase active phase active phase table 107. state of ports mode program memory ale psen port0 port1 port2 port3 porti2 idle internal 1 1 port data (1) port data port data port data port data idle external 1 1 floating port data address port data port data power-down internal 0 0 port dat* port data port data port data port data power-down external 0 0 floating port data port data port data port data
144 at8xc5122/23 4202b ? scr ? 07/03 usb interface suspend the suspend state can be detected by the usb controller if all the clocks are enabled and if the usb controller is enabled. the bit spint is set by hardware when an idle state is detected for more than 3 ms. this triggers a usb interrupt if enabled. in order to reduce current consumption, the firmware can put the usb pad in idle mode, stop the clocks and put the c51 in idle or power-down mode. the resume detection is still active. the usb pad is put in idle mode when the firmware clear the spint bit. in order to avoid a new suspend detection 3ms later, the firmware has to disable the usb clock input using the suspclk bit in the usbcon register. the usb pad automatically exits of idle mode when a wake-up event is detected. the stop of the 48 mhz clock from the pll should be done in the following order: 1. disable of the 48 mhz clock input of the usb controller by setting to 1 the sus- pclk bit in the usbcon register. 2. disable the pll by clearing the pllen bit in the pllcon register. resume when the usb controller is in suspend state, the resume detection is active even if all the clocks are disabled and if the c51 is in idle or power-down mode. the wupcpu bit is set by hardware when a non-idle state occurs on the usb bus. this triggers an inter- rupt if enabled. this interrupt wakes up the cpu from its idle or power-down state and the interrupt function is then executed. the firmware will first enable the 48 mhz gener- ation and then reset to 0 the suspclk bit in the usbcon register if needed. the firmware has to clear the spint bit in the usbint register before any other usb operation in order to wake up the usb controller from its suspend mode. the usb controller is then re-activated. figure 87. example of a suspend/resume management usb controller init detection of a suspend state spint set suspclk disable pll microcontroller in power-down detection of a resume state wupcpu enable pll clear suspclk clear wupcpu bit clear spint
145 at8xc5122/23 4202b ? scr ? 07/03 smart card interface entering in power-down mode in order to reduce the power consumption, a power-down or idle mode can be invoked by software (see table 13, pcon register). before activating these modes the applica- tion will need to: power-off the smart card interface by applying the following sequence: set crst pin at low level by clearing the bit cardrst in sccon register. set cclk pin at low level by clearing the bit clk then the cardclk in sccon register. set cio pin at low level by clearing the bit uart in scicr register then the bit cardio in sccon register. power the smart interface off by clearing the cardvcc bit in sccon register. this instruction enables to switch dc/dc converter off. cpres input: set the bit prsen in isel register set the bit ex1 in ie0 register set the bit ea in the ie0 register invert the bit cplev in isel register (int1 interrupt vector) clear the bit presit in the isel register exiting from power-down mode the microcontroller will exit from power-down or idle modes upon a reset or int1 inter- rupt which is a multiplexing of the interruptions generated by the cpres pin (card detection), rxd flag (uart reception) and int1 pin. keyboard interface only for at8xc5122. entering in power-down mode in order to reduce the power consumption, the microcontroller can be set in power-down or idle mode by software (see table 13, pcon register). before activating these modes the application will need to configure the keyboard interface as follows: set all keyboard ? s ouputs pins kb rx at low level by writing a 0 on the ports. this operation has a double effect: ? any key that is pressed generates an interrupt capable of waking-up the microcontroller, ? set all bits kbe.x in kbe registers to enable interrupts. exiting from power-down mode the microcontroller will exit from power-down mode upon a reset or any interrupt gener- ated by a key press. note that 1024 clocks are necessary to exit from power-down mode when a keyboard interrupt occurs. this means that there will be a delay between the time at which the key is pressed and the time at which the application is able to identify the key.
146 at8xc5122/23 4202b ? scr ? 07/03 registers reset value = 0xxx x000b table 108. auxiliary register - auxr (8eh) 76543210 dpu - - - xrs0 extram ao bit number bit mnemonic description 7dpu disable weak pull-up reset weak pull-up is enable set weak pull-up is disable 6-3 - reserved the value read from this bit is indeterminate. do not change these bits. 2xrs0 xram size 0 256 bytes (default) 1 512 bytes 1extram extram bit cleared to access internal xram using movx @ ri/ @ dptr. set to access external memory. programmed by hardware after power-up regarding hardware security byte (hsb), default setting , xram selected. 0ao ale output bit cleared , ale is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if x2 mode is used)(default). set , ale is active only during a movx or movc instructione is used.
147 at8xc5122/23 4202b ? scr ? 07/03 reset value = 00x1 0000b power-off flag reset value will be 1 only after a power on (cold reset). a warm reset doesn ? t affect the value of this bit. table 109. power control register - pcon (s:87h) 76543210 smod1 smod0 - pof gf1 gf0 pd idl bit number bit mnemonic description 7smod1 serial port mode bit 1 for uart set to select double baud rate in mode 1,2 or 3 6smod0 serial port mode bit 0 for uart cleared to select sm0 bit in scon register set to select fe bit in scon register 5- reserved the value read from this bit is indeterminate. do not change this bit. 4pof power-off flag cleared to recognize next reset type set by hardware when vcc rises from 0 to its nominal voltage. can also be set by software 3gf1 general purpose flag cleared by user for general-purpose usage set by user for general-purpose usage 2gf0 general purpose flag cleared by user for general-purpose usage set by user for general-purpose usage 1pd power-down mode bit cleared by hardware when reset occurs set to enter power-down mode 0idl idle mode bit cleared by hardware when interrupt or reset occurs set to enter idle mode
148 at8xc5122/23 4202b ? scr ? 07/03 data memory management expanded ram (xram) the at8xc5122/23 and at8xc5123 provides additional bytes of random access mem- ory (ram) space for increased data parameter handling and high level language usage. at8xc5122/23 and at8xc5123 devices have expanded ram in external data space; maximum size and location are described in table 110. the at8xc5122/23 and at8xc5123 have internal data memory that is mapped into four separate segments. the four segments are: the lower 128 bytes of ram (addresses 00h to 7fh) are directly and indirectly addressable. the upper 128 bytes of ram (addresses 80h to ffh) are indirectly addressable only. the special function registers, sfrs, (addresses 80h to ffh) are directly addressable only. the expanded ram bytes are indirectly accessed by movx instructions, and with the extram bit cleared in the auxr register (see table 108 on page 146) the lower 128 bytes can be accessed by either direct or indirect addressing. the upper 128 bytes can be accessed by indirect addressing only. the upper 128 bytes occupy the same address space as the sfr. that means they have the same address, but are physically separate from sfr space. table 110. description of expanded ram xram size address start end at8xc5122 and at8xc5123 512 00h 1ffh
149 at8xc5122/23 4202b ? scr ? 07/03 figure 88. internal and external data memory address when an instruction accesses an internal location above address 7fh, the cpu knows whether the access is in the upper 128 bytes of data ram or to sfr space by the addressing mode used in the instruction. instructions that use direct addressing access sfr space. for example: mov 0a0h, # data, accesses the sfr at location 0a0h (which is p2). instructions that use indirect addressing access the upper 128 bytes of data ram. for example: mov @r0, # data where r0 contains 0a0h, accesses the data byte at address 0a0h, rather than p2 (whose address is 0a0h). the xram bytes can be accessed by indirect addressing, with extram bit cleared and movx instructions. this part of memory which is physically located on-chip, logically occupies the first bytes of external data memory. the bit xrs0 is used to hide a part of the available xram as explained in table 108 on page 146. this can be useful if external peripherals are mapped at addresses already used by the internal xram. with extram = 0, the xram is indirectly addressed, using the movx instruction in combination with any of the registers r0, r1 of the selected bank or dptr. a n access to xram will not affect ports p0, p2, p3.6 (wr) and p3.7 (rd). for example, with extram = 0, movx @r0, # data where r0 contains 0a0h, accesses the xram at address 0a0h rather than external memory. an access to external data memory locations higher than the accessible size of the xram will be performed with the movx dptr instructions in the same way as in the standard 80c51, with p0 and p2 as data/address busses, and p3.6 and p3.7 as write and read timing signals. accesses to xram above 0ffh can only be done by the use of dptr. xram upper 128 bytes internal ram lower 128 bytes internal ram special function register 80h 80h 00 1ffh 0ffh 00 0ffh external data memory 0000 00ffh up to 03ffh 0ffffh indirect accesses direct accesses direct or indirect accesses 7fh
150 at8xc5122/23 4202b ? scr ? 07/03 with extram = 1 , movx @ri and movx @dptr will be similar to the standard 80c51. movx @ ri will provide an eight-bit address multiplexed with data on port 0 and any output port pins can be used to output higher order address bits. this is to provide the external paging capability. movx @dptr will generate a sixteen-bit address. port 2 outputs the high-order eight address bits (the contents of dph) while port0 multiplexes the low-order eight address bits (dpl) with data. movx @ ri and movx @dptr will generate either read or write signals on p3.6 (wr ) and p3.7 (rd ). the stack pointer (sp) may be located anywhere in the 256 bytes ram (lower and upper ram) internal data memory. the stack may not be located in the xram. the m0 bit allows to stretch the xram timings; if m0 is set, the read and write pulses are extended from 6 to 30 clock periods. this is useful to access external slow peripherals. dual data pointer register (ddptr) the additional data pointer can be used to speed up code execution and reduce code size. the dual dptr structure is a way by which the chip will specify the address of an exter- nal data memory location. there are two 16-bit dptr registers that address the external memory, and a single bit called dps = auxr1.0 (see table 112) that allow the program code to switch between them (figure 89). figure 89. use of dual pointer a. bit 2 stuck at 0; this allows to use inc auxr1 to toggle dps without changing gf3. external data memory auxr1(a2h) dps dph(83h) dpl(82h) 0 7 dptr0 dptr1
151 at8xc5122/23 4202b ? scr ? 07/03 assembly language ; block move using dual data pointers ; modifies dptr0, dptr1, a and psw ; note: dps exits opposite of entry state ; unless an extra inc auxr1 is added ; 00a2 auxr1 qu 0a2h ; 0000 909000mov dptr,#source ; address of source 0003 05a2 inc auxr1 ; switch data pointers 0005 90a000 mov dptr,#dest ; address of dest 0008 loop: 0008 05a2 inc auxr1 ; switch data pointers 000a e0 movx a,@dptr ; get a byte from source 000b a3 inc dptr ;increment source address 000c 05a2 inc auxr1 ; switch data pointers 000e f0 movx @dptr,a ; write the byte to dest 000f a3 inc dptr ; increment dest address 0010 70f6jnz loop ; check for 0 terminator 0012 05a2 inc auxr1 ; (optional) restore dps inc is a short (2 bytes) and fast (12 clocks) way to manipulate the dps bit in the auxr1 sfr. however, note that the inc instruction does not directly force the dps bit to a par- ticular state, but simply toggles it. in simple routines, such as the block move example, only the fact that dps is toggled in the proper sequence matters, not its actual value. for example, the block move routine works the same whether dps is ? 0 ? or ? 1 ? on entry. observe that without the last instruction (inc auxr1), the routine will exit with dps in the opposite state. registers see table 108 on page 146 for the definition of auxr register. table 111. auxiliary register 1 auxr1- (0a2h) for at8xc5122 reset value = xx1x xx0x0b (not bit addressable) 7 6 5 4 3 2 1 0 --enboot-gf30-dps bit number bit mnemonic description 7 - 6 - reserved the value read from this bit is indeterminate. do not change these bits. 5enboot enable boot rom (rom/cram version only) set this bit to map the boot rom from 8000h to ffffh. if the pc increments beyond 7fffh address, the code is fetch from internal rom clear this bit to disable boot rom. if the pc increments beyond 7fffh address, the code is fetch from external code memory (c51 standard roll over function) this bit is forced to 1 at reset 4- reserved the value read from this bit is indeterminate. do not change this bit. 3 gf3 this bit is a general-purpose user flag. 2 0 always cleared. 1- reserved the value read from this bit is indeterminate. do not change this bit. 0dps data pointer selection cleared to select dptr0. set to select dptr1.
152 at8xc5122/23 4202b ? scr ? 07/03 table 112. auxiliary register 1 auxr1- (0a2h) for at8xc5123 reset value = xxxx xx0x0b (not bit addressable) 7 6 5 4 3 2 1 0 ----gf30-dps bit number bit mnemonic description 7 - 6 - reserved the value read from this bit is indeterminate. do not change these bits. 5 reserved the value read from this bit is indeterminate. do not change these bits. 4- reserved the value read from this bit is indeterminate. do not change this bit. 3 gf3 this bit is a general-purpose user flag. 2 0 always cleared. 1- reserved the value read from this bit is indeterminate. do not change this bit. 0dps data pointer selection cleared to select dptr0. set to select dptr1.
153 at8xc5122/23 4202b ? scr ? 07/03 program memory management the at8xc5122/23 will be available in two configurations: cram / rom rom both configurations provide: ? 32k bytes of internal rom (only 30k bytes for at8xc5123) ? 256 bytes of ram ? 512 bytes of internal xram the cram/rom configuration contain an isp software (bootloader) and a rom moni- tor (emulator) mainly dedicated for pre-production, code development and debug, or specific applications while the rom configuration contains the final customer application.
154 at8xc5122/23 4202b ? scr ? 07/03 rom configuration register the rom configuration register is masked and is not accessible by the mcu. it con- tains fuse bits which enable the product configuration. table 113. rom configuration register for at8xc5122 table 114. rom configuration register for at8xc5123 76543210 bljrb lb2 lb1 lb0 bit number bit mnemonic description 7- reserved 6bljrb bootloader jump rom bit set to configure user code in rom with a reset@0000h clear to configure in cram/rom (bootloader mode with a reset@f800h) 5 - 3 - reserved 2 - 0 lb2:0 program lock bits the program lock bits protects the on-chip program against software piracy. the at8xc5122 products are delivered with the lowest protection level as detailed in the following table: lb2 lb1 lb0 security level protection description 111 1 no program lock features enabled. 101 2 read test mode function is disabled. high pin count package movc instruction executed from external program memory are disabled from fetching code bytes from internal memory. ea is sampled and latched on reset. external execution is enabled. checksum control is enabled. low pin count package checksum control is enabled. 76543210 -----lb2lb1lb0 bit number bit mnemonic description 7 - 3 - reserved
155 at8xc5122/23 4202b ? scr ? 07/03 2 - 0 lb2:0 program lock bits the program lock bits protects the on-chip program against software piracy. the at8xc5122 products are delivered with the lowest protection level as detailed in the following table: lb2 lb1 lb0 security level protection description 111 1 no program lock features enabled. 101 2 read test mode function is disabled. high pin count package movc instruction executed from external program memory are disabled from fetching code bytes from internal memory. ea is sampled and latched on reset. external execution is enabled. checksum control is enabled. low pin count package checksum control is enabled. bit number bit mnemonic description
156 at8xc5122/23 4202b ? scr ? 07/03 cram/rom configuration the split of internal memory spaces depends on the product and is detailed below. the instruction codes are fetched from external or internal program memory depending on the logic state of microcontroller ? s ea pin. only valid for high pin count packages (vqfp64). case ea = 0 after the reset, the program counter is initialised to 0000h and the code instructions are fetched from external program memory. case ea = 1 the rom contains the bootloader code. after reset sequence the program counter is initialized to f800h and the bootloader is run. the bootloader downloads the application into the cram. the sources to download the application from are in priority: an external 32k eeprom attached to a synchronous serial interface a host attached to a usb interface a host attached to a rs232c interface note: since the rom is mapped in the upper 32k of program memory, the bootloader is not able to provide direct interrup services. rollover function once the application is running in the internal lower 32k memory space, it can roll over in the external upper 32k memory space. a bit called enboot and contained in auxr1 register enables to select this function. enboot bit is set to 1 by the reset function. mapping the program memory space is described in figure 90.
157 at8xc5122/23 4202b ? scr ? 07/03 figure 90. rom contents (cram / rom configuration) 8000 ffff c000 bfff 7fff 0000 cram reserved rom bootloader
158 at8xc5122/23 4202b ? scr ? 07/03 rom configuration the product provides the following program and data memory spaces. the instruction codes are fetched from external or internal program memory depending on the logic state of microcontroller ? s ea pin. only valid for high pin count packages (vqfp64). case ea = 0 after the reset the program counter is initialised to 0000h and the code instructions are fetched from external program memory. case ea = 1 after a reset the program counter is initialized to 0000h and the customer application contained in internal rom is executed from address 0000h to 7fffh. the program memory space is described in figure below: figure 91. rom contents (rom configuration) memory mapping in the products rom versions, the following internal spaces are defined: ram xram cram: 32k bytes program ram memory rom the specific accesses from/to these memories are: xram: if the bit rps in rcon (described below) is reset, movx instructions address the xram space. cram: if the bit rps in rcon is set, movx instructions address the cram space. reset@<0000> rom configuration 7fff rom user code
159 at8xc5122/23 4202b ? scr ? 07/03 reset value = xxxx 0xxxb cram version without customer mask two memory blocks are implemented: the rom memory contains the bootloader program. the cram is the application program memory. after a reset, the program is downloaded, as described above, from: either an external eeprom, or from an host conected on rs232 serial link. into the program cram memory of 32k bytes. then the program counter is set at address 0000h of the cram space and the program is executed. figure 92. cram+rom mapping table 115. ram configuration register - rcon (d1h) 76543210 ----rps--- bit number bit mnemonic description 7 - 4 - reserved the value read from this bit is indeterminate. do not change these bits. 3rps cram space map bit set to map the cram space during movx instructions clear to map the data space during movx. this bit has priority over the extram bit. 2-0 - reserved the value read from this bit is indeterminate. do not change these bits. 32k 512b 0000h 7fffh cram xram ram rom ffffh 256b 8000h bootloade r f800h entry point
160 at8xc5122/23 4202b ? scr ? 07/03 cram version with customer mask and rom version in this version, the customer program is masked in 32k bytes rom. two memory areas are implemented: the customer program is masked in rom during the final production phase. the rom size will be determinated at mask generation process depending of the program size. in the cram+rom product, the cram is not used. the bootloader jump rom bit (bljrb) is set to enable the user rom program which is executed after reset.
161 at8xc5122/23 4202b ? scr ? 07/03 electrical characteristics absolute maximum ratings dc parameters t a = -40 to +85 c; v ss = 0 v, f= 0 to 16mhz x2 core v cc = 3.6v to 5.5v on -m version ambiant temperature under bias ......................-25 c to 85 c storage temperature .................................... -65 c to + 150 c voltage on v cc to v ss ......................................-0.5 v to + 6.0v voltage on any pin to v ss ........................-0.5 v to v cc + 0.5 v power dissipation tbd w note: stresses at or above those listed under ? absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions may affect device reliability. power dissipation value is based on the maximum allowable die temperature and the thermal resistance of the package. table 116. core dc parameters (xtal, rst , p0, p2, p3, p4, p5, ale, psen , ea ) symbol parameter min typ max unit test conditions v il input low voltage -0.5 0.2 v cc - 0.1 v v ih input high voltage except xtal1, rst 0.2 v cc + 0.9 v cc + 0.5 v v ih1 input high voltage, xtal1, rst 0.7 v cc v cc + 0.5 v v ol output low voltage: p0, ale, psen 0.45 v i ol = 1.6 ma v oh output high voltage: p0, ale, psen 0.9 v cc vi oh = -40 a v ol1 output low voltage: p2, p3, p4, p5, p1.2, p1.6, p1.7, 0.45 v i ol = 0.8 ma v oh1 output high voltage: p2, p3, p4, p5, p1.2, p1.6, p1.7 0.9 v cc vi oh = -10 a i il logical 0 input current ports 2 to 5 and p1.2, p1.6, p1.7, if weak pull-up enabled -50 a vin = 0.45 v i li input leakage current 10 a 0.45 v < v in < v cc i tl logical 1 to o transistion current, port 51 configuration ? 650 av in = 2 v r medium medium pullup resistor 10 k ? r weak weak pullup resistor 100 k ? cio capacitance of i/o buffer 10 pf fc = 1 mhz t a = 25 c cio capacitance of i/o buffer 10 pf fc = 1 mhz t a = 25 c di cc digital supply output current 10 ma c l = 100 nf f= 16 mhz x1 dv cc digital supply voltage 3 3.3 3.6 v c l = 100 nf
162 at8xc5122/23 4202b ? scr ? 07/03 operating i cc test condition figure 93. i cc test condition, idle mode figure 94. i cc test condition, power-down mode figure 95. clock signal waveform for i cc tests in idle mode v pfdp power fail high level threshold 2.8 v v pfdm power fail low level threshold 2.6 v t rise, t fall v dd rise and fall time 1 s 600 second r rst internal reset pull-up resistor 15 k ? c external reset capacitor 150 nf 1 f trst reset duration 10 70 ms trst=0.7*r*c table 116. core dc parameters (xtal, rst , p0, p2, p3, p4, p5, ale, psen , ea ) (continued) symbol parameter min typ max unit test conditions all other pins are disconnected . reset = v cc after a high pulse during at least 24 clock cycles ea (nc) clock signal vss xtal1 xtal2 v cc v cc rst v cc icc v cc p0 all other pins are disconnected. reset = v cc after a high pulse during at least 24 clock cycles v cc rst ea v cc icc v cc v cc (nc) p0 xtal2 xtal1 vss v cc -0.5v 0.45v 0.7v cc 0.2v cc -0.1 t clch t chcl t clch = t chcl = 5 ns.
163 at8xc5122/23 4202b ? scr ? 07/03 figure 96. i cc test condition, active mode led ? s note: 1. (t a = -20 c to +50 c, v cc - v ol = 2 v 20%) smart card interface all other pins are disconnected. reset = v cc after a high pulse during at least 24 clock cycles v cc rst ea v cc icc v cc v cc (nc) p0 xtal2 xtal1 vss v cc clock signal table 117. led outputs dc parameters symbol parameter min typ max unit test conditions i ol output low current, p3.6 and p3.7 led modes 1 2 5 2 4 10 4 8 20 ma ma ma 2 ma configuration 4 ma configuration 10 ma configuration table 118. smart card 5v interface dc parameters symbol parameter min typ max unit test conditions ci cc card supply current 60 121 105 102 ma vcc = 5.5v vcc = 4v vcc = 2.85v cv cc card supply voltage 4.6 5.4 v cicc = 60 ma ripple on vcard 200 mv 0 < cicc < 60 ma cv cc spikes on vcard 4.6 5.4 v maxi. charge 20 na max. duration 400 ns max. variation cicc 100 ma t vhll vcard to 0 750 s cicc = 0 vcard = 5v to 0.4v table 119. smart card 3v interface dc parameters symbol parameter min typ max unit test conditions ci cc card supply current 60 110 89 110 ma vcc = 5.5v vcc = 4v vcc = 2.85v cv cc card supply voltage 2.76 3.24 v cicc = 60 ma ripple on vcard 200 mv 0 < cicc < 60 ma cv cc spikes on vcard 2.76 3.24 v maxi. charge 10na.s max. duration 400 ns max. variation cicc 50ma
164 at8xc5122/23 4202b ? scr ? 07/03 notes: 1. test conditions, capacitor 10 f, inductance 10 h. 2. ceramic x7r, smd type capacitor with minimum esr or 250 m ? is mandatory note: 1. the voltage on clk should remain between -0.3v and v cc +0.3v during dynamic operation t vhll cvcc to 0 750 s icard=0 vcard = 5v to 0.4v table 119. smart card 3v interface dc parameters symbol parameter min typ max unit test conditions table 120. smart card 1.8v interface dc parameters symbol parameter min typ max unit test conditions ci cc card supply current 20 109 100 82 ma vcc = 5.5v vcc = 4v vcc = 2.85v cv cc card supply voltage 1.68 1.92 v cicc = 20 ma cv cc spikes on vcard 1.68 1.92 v t vhll cvcc to 0 750 s cicc = 0 cv cc = 5v to 0.4v table 121. smart card clock dc parameters (port p1.4) symbol parameter min typ max unit test conditions v ol output low voltage 0 (1) 0 (1) 0.2xv cc 0.4 vi ol = 20 ? (1.8v, 3v) i ol = 50 a (5v) i ol output low current 15 ma v oh output high voltage 0.7 cv cc 0.7 cv cc 0.7 cv cc cv cc - 0.5 cv cc cv cc cv cc cv cc v v v v i oh = 20 a (1.8v) i oh = 20 a (3v) i oh = 20 a (5v) i oh = 50 a (5v) i oh output high current 15 ma t r t f rise and fall delays 16 22.5 50 ns c in =30pf (5v) c in =30pf (3v) c in =30pf (1.8v) voltage stability -0.25 cv cc -0.5 0.4 cv cc cv cc + 0.25 v low level high level frequency variation 1% cycle ratio 45% 55% table 122. smart card i/o dc parameters (p1.0) symbol parameter min typ max unit test conditions v il input low voltage 0 (1) 0 (1) 0.5 0.15 cv cc vi il = 500 a i il = 20 a i il input low current 500 a
165 at8xc5122/23 4202b ? scr ? 07/03 note: 1. the voltage on rst should remain between -0.3v and v cc +0.3v during dynamic operation. note: 1. the voltage on rst should remain between -0.3v and v cc +0.3v during dynamic operation. v ih input high voltage 0.7 cv cc cv cc vi ih = -20 a i ih input high current -20 / +20 a v ol output low voltage 0 (1) 0.4 0.4 0.3 v i ol = 1ma (5v) i ol = 1ma (3v) i ol = 1ma (1.8v) i ol output low current 15 ma v oh output high voltage 0.8 cv cc 0.7 cv cc cv cc (1) v i oh = 20 a (5v) i oh = 20 a (3v, 1.8v) i oh output high current 15 ma voltage stability -0.25 0.8 cv cc 0.4 cv cc + 0.25 v low level high level t r t f rise and fall delays 0.8 sc in =30pf table 122. smart card i/o dc parameters (p1.0) (continued) symbol parameter min typ max unit test conditions table 123. smart card rst, cc4, cc8, dc parameters (port p1.5, p1.3, p1.1) symbol parameter min typ max unit test conditions v ol output low voltage 0 (1) 0 (1) 0.12 x v cc 0.4 v i ol = 20 ? i ol = 50 ? i ol output low current 15 ma v oh output high voltage cv cc - 0.5 0.8 x v cc cv cc cv cc (1) vi oh = 50 ? i oh = 20 ? i oh output high current 15 ma t r t f rise and fall delays 0.8 sc in =30 pf voltage stability -0.25 cv cc -0.5 0.4 x cv cc cv cc + 0.25 low level high level table 124. card presence dc parameters (p1.2) symbol parameter min typ max unit test conditions i ol1 cpres weak pull-up output current 3 10 25 a p1.2=1, short to vss pull-up enabled
166 at8xc5122/23 4202b ? scr ? 07/03 usb interface figure 97. usb interface ac parameters explanation of the ac symbols each timing symbol has 5 characters. the first character is always a ? t ? (stands for time). the other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. the following is a list of all the characters and what they stand for. example:t avll = time for address valid to ale low. t llpl = time for ale low to psen low. t a = -40 c to +85 c; v ss = 0v; v cc = 5v 10%; f = 0 to 40 mhz. (load capacitance for port 0, ale and psen = 60 pf; load capacitance for all other outputs = 60 pf.) table 125, table 128 and table 131 give the description of each ac symbols. table 126, table 130 and table 132 give for each range the ac parameter. table 127, table 130 and table 133 give the frequency derating formula of the ac parameter for each speed range description. to calculate each ac symbols. take the x value and use this value in the formula. example: t lliv and 20 mhz, standard clock. x = 30 ns t = 50 ns t cciv = 4t - x = 170 ns symbol parameter min typ (5) max unit v ref usb reference voltage 3.0 3.6 v v ih input high voltage for d+ and d- (driven) 2.0 v v ihz input high voltage for d+ and d- (floating) 2.7 3.6 v v il input low voltage for d+ and d- 0.8 v v oh output high voltage for d+ and d- 2.8 3.6 v v ol output low voltage for d+ and d- 0.0 0.3 v 1 4 2 3 1- v bus 2 - d - 3 - d + 4 - gnd usb ? b ? receptacle v ref d + d - r rpad rpad r = 1.5 k ? r pad = 27 ?
167 at8xc5122/23 4202b ? scr ? 07/03 external program memory characteristics table 125. symbol description symbol parameter t oscillator clock period t lhll ale pulse width t av ll address valid to ale t llax address hold after ale t lliv ale to valid instruction in t llpl ale to psen t plph psen pulse width t pliv psen to valid instruction in t pxix input instruction hold after psen t pxiz input instruction float after psen t aviv address to valid instruction in t plaz psen low to address float table 126. ac parameters for a fix clock (f = 40 mhz) symbol min max units ttbd ns t lhll tbd ns t avll tbd ns t llax tbd ns t lliv tbd ns t llpl tbd ns t plph tbd ns t pliv tbd ns t pxix tbd ns t pxiz tbd ns t aviv tbd ns t plaz tbd ns
168 at8xc5122/23 4202b ? scr ? 07/03 table 127. ac parameters for a variable clock external program memory read cycle symbol type standard clock x2 clock x parameter units t lhll min 2 t - x t - x 10 ns t avll min t - x 0.5 t - x 15 ns t llax min t - x 0.5 t - x 15 ns t lliv max 4 t - x 2 t - x 30 ns t llpl min t - x 0.5 t - x 10 ns t plph min 3 t - x 1.5 t - x 20 ns t pliv max 3 t - x 1.5 t - x 40 ns t pxix min x x 0 ns t pxiz max t - x 0.5 t - x 7 ns t aviv max 5 t - x 2.5 t - x 40 ns t plaz max x x 10 ns 12 t clcl t lliv t lhll t llpl ale t plph psen port 0 instr in a0-a7 instr in a0-a7 instr in t llax tplaz t pxav t avll t pxix t pxiz t pliv t aviv port 2 address or sfr-p2 address a8-a15 address a8-a15
169 at8xc5122/23 4202b ? scr ? 07/03 external data memory characteristics table 128. symbol description table 129. ac parameters for a variable clock (f = 40 mhz) symbol parameter t rlrh rd pulse width t wlwh wr pulse width t rldv rd to valid data in t rhdx data hold after rd t rhdz data float after rd t lldv ale to valid data in t avdv address to valid data in t llwl ale to wr or rd t avw l address to wr or rd t qvwx data valid to wr transition t qvwh data set-up to wr high t whqx data hold after wr t rlaz rd low to address float t whlh rd or wr high to ale high symbol min max units t rlrh tbd ns t wlwh tbd ns t rldv tbd ns t rhdx tbd ns t rhdz tbd ns t lldv tbd ns t avdv tbd ns t llwl tbd tbd ns t avwl tbd ns t qvwx tbd ns t qvwh tbd ns t whqx tbd ns t rlaz tbd ns t whlh tbd tbd ns
170 at8xc5122/23 4202b ? scr ? 07/03 table 130. ac parameters for a variable clock external data memory write cycle symbol type standard clock x2 clock x parameter units t rlrh min 6 t - x 3 t - x 20 ns t wlwh min 6 t - x 3 t - x 20 ns t rldv max 5 t - x 2.5 t - x 25 ns t rhdx min x x 0 ns t rhdz max 2 t - x t - x 20 ns t lldv max 8 t - x 4t -x 40 ns t avdv max 9 t - x 4.5 t - x 60 ns t llwl min 3 t - x 1.5 t - x 25 ns t llwl max 3 t + x 1.5 t + x 25 ns t avwl min 4 t - x 2 t - x 25 ns t qvwx min t - x 0.5 t - x 15 ns t qvwh min 7 t - x 3.5 t - x 25 ns t whqx min t - x 0.5 t - x 10 ns t rlaz max x x 0 ns t whlh min t - x 0.5 t - x 15 ns t whlh max t + x 0.5 t + x 15 ns t qvwh t llax ale psen wr port 0 port 2 a0-a7 data out address or sfr-p2 t avw l t llwl t qvwx address a8-a15 or sfr p2 t whqx t whlh t wlwh
171 at8xc5122/23 4202b ? scr ? 07/03 external data memory read cycle serial port timing - shift register mode table 131. symbol description (f = 40 mhz) table 132. ac parameters for a fix clock (f = 40 mhz) table 133. ac parameters for a variable clock shift register timing waveform ale psen rd port 0 port 2 a0-a7 data in address or sfr-p2 t avwl t llwl t rlaz address a8-a15 or sfr p2 t rhdz t whlh t rlrh t lldv t rhdx t llax t avdv symbol parameter t xlxl serial port clock cycle time t qvhx output data set-up to clock rising edge t xhqx output data hold after clock rising edge t xhdx input data hold after clock rising edge t xhdv clock rising edge to input data valid symbol min max units t xlxl tbd ns t qvhx tbd ns t xhqx tbd ns t xhdx tbd ns t xhdv tbd ns symbol type standard clock x2 clock x parameter for -m range units t xlxl min 12 t 6 t ns t qvhx min 10 t - x 5 t - x 50 ns t xhqx min 2 t - x t - x 20 ns t xhdx min x x 0 ns t xhdv max 10 t - x 5 t- x 133 ns
172 at8xc5122/23 4202b ? scr ? 07/03 external clock drive characteristics (xtal1) table 134. ac parameters external clock drive waveforms ac testing input/output waveforms ac inputs during testing are driven at v cc - 0.5 for a logic ? 1 ? and 0.45v for a logic ? 0 ? . timing measurement are made at v ih min for a logic ? 1 ? and v il max for a logic ? 0 ? . float waveforms for timing purposes as port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loaded v oh /v ol level occurs. i ol /i oh 20 ma. valid valid valid valid valid valid input data valid 0123456 8 7 ale clock output data write to sbuf clear ri t xlxl t qvxh t xhqx t xhdv t xhdx set ti set ri instruction 01234567 valid symbol parameter min max units t clcl oscillator period 25 ns t chcx high time 5 ns t clcx low time 5 ns t clch rise time 5 ns t chcl fall time 5 ns t chcx /t clcx cyclic ratio in x2 mode 40 60 % v cc -0.5v 0.45v 0.7v cc 0.2v cc -0.1 t chcl t clcx t clcl t clch t chcx input/output 0.2 v cc + 0.9 0.2 v cc - 0.1 v cc -0.5v 0.45v float v oh - 0.1 v v ol + 0.1 v v load v load + 0.1 v v load - 0.1 v
173 at8xc5122/23 4202b ? scr ? 07/03 clock waveforms valid in normal clock mode. in x2 mode xtal2 must be changed to xtal2/2. this diagram indicates when signals are clocked internally. the time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. this propagation delay is dependent on variables such as temperature and pin loading. propagation also varies from output to output and component. typically though (t a =25 c fully loaded) rd and wr propagation delays are approximately 50 ns. the other signals are typically 85 ns. propagation delays are incorporated in the ac specifications. data pcl out data pcl out data pcl out sampled sampled sampled state4 state5 state6 state1 state2 state3 state4 state5 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 float float float these signals are not activated during the execution of a movx instruction indicates address transitions external program memory fetch float data sampled dpl or rt out indicates dph or p2 sfr to pch transition pcl out (if program memory is external) pcl out (even if program memory is internal) pcl out (if program memory is external old data new data p0 pins sampled p1, p2, p3 pins sampled p1, p2, p3 pins sampled p0 pins sampled rxd sampled internal clock xtal2 ale psen p0 p2 (ext) read cycle write cycle rd p0 p2 wr port operation mov port src mov dest p0 mov dest port (p1. p2. p3) (includes into. int1. to t1) serial port shift clock txd (mode 0) data out dpl or rt out indicates dph or p2 sfr to pch transition p0 p2 rxd sampled
174 at8xc5122/23 4202b ? scr ? 07/03 usb interface rise time fall time v crs differential data lines 90% 10% 90% 10% t r t f v hmin v lmax table 135. usb ac parameters symbol parameter min typ (5) max unit t r rise time 4 20 ns t f fall time 4 20 ns t fdrate full-speed data rate 11.9700 12.0300 mb/s v crs crossover voltage 1.3 2.0 v t dj1 source jitter total to next transaction -3.5 3.5 ns t dj2 source jitter total for paired transactions -4 4 ns t jr1 receiver jitter to next transaction -18.5 18.5 ns t jr2 receiver jitter for paired transactions -9 9 ns
175 at8xc5122/23 4202b ? scr ? 07/03 typical application figure 98. typical smart card reader and keyboard application schematic gnd 100 nf vcc v ref xtal1 xtal2 li cvcc cpres crst cclk cc4 cc8 cio + 10 uf cvss cvss i/o c8 c4 clk rst gnd gnd gnd d- ledx master card i/o rst clk cio1 crst1 cclk1 vcc 1 m ? (optional resistor) pllf d+ p0 p2 p4 p5 scan output gnd 1.5 k ? cvss 10 h 470 nf dvcc gnd vcc 100 nf gnd gnd 22 pf 22 pf 8 mhz alternate card ea vcc rst 10 k ? + gnd (optional capacitor) digital master card master card card presence switch power supply reset avss vss power supply 100 nf avss analog power supply avcc gnd note 1: as close as possible from mcu line d+ line d- 27 ? 27 ? vcc scan output scan output scan input keyboard ground (note 1) (note 1) (note 1) (note 1) (note 1) (note 1) (note 1) (note 1) (note 1) (note 1) usb host
176 at8xc5122/23 4202b ? scr ? 07/03 figure 99. typical smart card reader application schematic gnd 100 nf vcc v ref xtal1 xtal2 li cvcc cpres crst cclk cc4 cc8 cio + 10 uf cvss cvss i/o c8 c4 clk rst gnd gnd gnd d- ledx master card i/o rst clk cio1 crst1 cclk1 vcc 1 m ? (optional resistor) pllf d+ gnd 1.5 k ? cvss 10 h 470 nf dvcc gnd vcc 100 nf gnd gnd 22 pf 22 pf 8 mhz alternate card rst + gnd (optional capacitor) digital master card master card card presence switch power supply reset avss vss power supply 100 nf avss analog power supply avcc gnd note 1: as close as possible from mcu line d+ line d- 27 ? 27 ? vcc ground (note 1) (note 1) (note 1) (note 1) (note 1) (note 1) (note 1) (note 1) (note 1) (note 1) usb host
177 at8xc5122/23 4202b ? scr ? 07/03 ordering information part number memory size (bytes) supply voltage (v) temperature range max frequency (mhz) package packing at83c5122xxx-rdtim 32k rom 3.6 - 5.5 industrial 32 vqfp64 tray at83c5122xxx-rdrim 32k rom 3.6 - 5.5 industrial 32 vqfp64 tape & reel at83c5122xxx-sisim 32k rom 3.6 - 5.5 industrial 32 plcc28 stick at83c5122xxx-sirim 32k rom 3.6 - 5.5 industrial 32 plcc28 tape & reel at85ec5122-rdvim 32k rom + 512 bytes eeprom 3.6 - 5.5 industrial 32 vqfp64 tray & dry pack at85ec5122-rdfim 32k rom + 512 bytes eeprom 3.6 - 5.5 industrial 32 vqfp64 tray & reel & dry pack at85ec5122-siuim (1) 32k rom + 512 bytes eeprom 3.6 - 5.5 industrial 32 plcc28 stick & dry pack at85ec5122-sixim (1) 32k rom + 512 bytes eeprom 3.6 - 5.5 industrial 32 plcc28 tray & reel & dry pack at85c5122xxx-rdtim ram 3.6 - 5.5 industrial 32 vqfp64 tray at85c5122xxx-rdrim ram 3.6 - 5.5 industrial 32 vqfp64 tape & reel at85c5122xxx-sisim ram 3.6 - 5.5 industrial 32 plcc28 stick at85c5122xxx-sirim ram 3.6 - 5.5 industrial 32 plcc28 tape & reel AT89C5122-rdtim (1) 32k flash ram 3.6 - 5.5 industrial 32 vqfp64 tray AT89C5122-rdrim (1) 32k flash ram 3.6 - 5.5 industrial 32 vqfp64 tape & reel AT89C5122-sisim (1) 32k flash ram 3.6 - 5.5 industrial 32 plcc28 stick AT89C5122-sirim (1) 32k flash ram 3.6 - 5.5 industrial 32 plcc28 tape & reel at83c5123xxx-ratim 30k rom 3.6 - 5.5 industrial 32 lqfp32 tray at83c5123xxx-rarim 30k rom 3.6 - 5.5 industrial 32 lqfp32 tape & reel at83c5123xxx-sisim 30k rom 3.6 - 5.5 industrial 32 plcc28 stick at83c5123xxx-sirim 30k rom 3.6 - 5.5 industrial 32 plcc28 tape & reel at83ec5123xxx-ravim 30k rom + 512 bytes eeprom 3.6 - 5.5 industrial 32 lqfp32 tray & dry pack at83ec5123xxx-rafim 30k rom + 512 bytes eeprom 3.6 - 5.5 industrial 32 lqfp32 tray & reel & dry pack at83ec5123xxx-siuim (1) 30k rom + 512 bytes eeprom 3.6 - 5.5 industrial 32 plcc28 stick & dry pack
178 at8xc5122/23 4202b ? scr ? 07/03 note: 1. check avaibility with sales office at83ec5123xxx-sixim (1) 30k rom + 512 bytes eeprom 3.6 - 5.5 industrial 32 plcc28 tray & reel & dry pack part number memory size (bytes) supply voltage (v) temperature range max frequency (mhz) package packing
179 at8xc5122/23 4202b ? scr ? 07/03 packaging information plcc28
180 at8xc5122/23 4202b ? scr ? 07/03 vqfp64
181 at8xc5122/23 4202b ? scr ? 07/03 plcc68
182 at8xc5122/23 4202b ? scr ? 07/03 lqfp32
183 at8xc5122/23 4202b ? scr ? 07/03 datasheet change log changes from 4202a to 4122b 1. product at8xec5122 added. 2. products at83c5123 and at83ec5123 added.
i at8xc5122/23 4202b ? scr ? 07/03 table of contents features ................................................................................................. 1 description ............................................................................................ 2 at8xc5122 block diagram. ................................................................. 3 at8xc5123 block diagram. ................................................................. 3 pin description ..................................................................................... 4 .............................................................................................................................. 4 signals .................................................................................................................. 6 i/o port definition ............................................................................................... 10 port configuration............................................................................................... 13 registers............................................................................................................. 17 sfr description .................................................................................. 21 clock controller .................................................................................. 28 oscillator............................................................................................................. 32 pll ..................................................................................................................... 32 registers............................................................................................................. 34 smart card interface block (scib) .................................................... 37 block diagram .................................................................................................... 38 functional description ........................................................................................ 38 additional features............................................................................................. 43 registers............................................................................................................. 45 dc/dc converter................................................................................................ 54 usb controller .................................................................................... 57 description.......................................................................................................... 58 configuration ...................................................................................................... 61 read/write data fifo ........................................................................................ 64 bulk / interrupt transactions............................................................................... 65 control transactions........................................................................................... 69 isochronous transactions................................................................................... 70 miscellaneous ..................................................................................................... 72 suspend/resume management .........................................................................73 detach simulation............................................................................................... 75 usb interrupt system ......................................................................................... 76 registers............................................................................................................. 78 serial i/o port ...................................................................................... 88 framing error detection ..................................................................................... 88
ii at8xc5122/23 4202b ? scr ? 07/03 automatic address recognition.......................................................................... 89 asynchronous modes (modes 1, 2 and 3) .......................................................... 93 modes 2 and 3 .................................................................................................... 94 registers............................................................................................................. 97 serial port interface (spi) ................................................................... 99 features.............................................................................................................. 99 signal description............................................................................................... 99 functional description ...................................................................................... 101 timers/counters ............................................................................... 109 timer/counter operations ................................................................................ 109 timer 0.............................................................................................................. 109 timer 1.............................................................................................................. 112 registers........................................................................................................... 114 keyboard interface ........................................................................... 117 introduction ....................................................................................................... 117 description........................................................................................................ 117 registers........................................................................................................... 118 interrupt system ............................................................................... 121 int1 interrupt vector ........................................................................................ 123 registers........................................................................................................... 123 interrupt sources and vector addresses.......................................................... 134 reset and power monitor ................................................................. 135 reset ................................................................................................................ 135 power monitor................................................................................................... 137 watchdog timer ................................................................................ 139 watchdog timer during power-down mode and idle ....................................... 141 power management .......................................................................... 142 idle mode .......................................................................................................... 142 power-down mode............................................................................................ 142 reduced emi mode .......................................................................................... 143 usb interface ................................................................................................... 144 smart card interface ........................................................................................ 145 keyboard interface ........................................................................................... 145 registers........................................................................................................... 146 data memory management .............................................................. 148 expanded ram (xram)................................................................................... 148 dual data pointer register (ddptr) ............................................................... 150 assembly language ................................................................................. 151
iii at8xc5122/23 4202b ? scr ? 07/03 registers........................................................................................................... 151 program memory management ....................................................... 153 rom configuration register............................................................................. 154 cram/rom configuration ............................................................................... 156 rom configuration ........................................................................................... 158 memory mapping .............................................................................................. 158 electrical characteristics ................................................................. 161 absolute maximum ratings ..............................................................................161 dc parameters .................................................................................................161 ac parameters ................................................................................................. 166 float waveforms............................................................................................... 172 clock waveforms.............................................................................................. 173 typical application ........................................................................... 175 ordering information ........................................................................ 177 packaging information ..................................................................... 179 plcc28 ............................................................................................................ 179 vqfp64 ............................................................................................................ 180 plcc68 ............................................................................................................ 181 lqfp32 ............................................................................................................ 182 datasheet change log ..................................................................... 183 changes from 4202a to 4122b ........................................................................183
printed on recycled paper. disclaimer: atmel corporation makes no warranty for the use of its products, other than those expressly contained in the company ? s standard warranty which is detailed in atmel ? s terms and conditions located on the company ? s web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time wi thout notice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectual property of atmel are granted by the company in connection with the sale of atmel products, expressly or by implication. atmel ? s products are not authorized for use as critical components in life support devices or systems. atmel corporation atmel operations 2325 orchard parkway san jose, ca 95131 tel: 1(408) 441-0311 fax: 1(408) 487-2600 regional headquarters europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel: (41) 26-426-5555 fax: (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131 tel: 1(408) 441-0311 fax: 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131 tel: 1(408) 441-0311 fax: 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel: (33) 2-40-18-18-18 fax: (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel: (33) 4-42-53-60-00 fax: (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel: 1(719) 576-3300 fax: 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel: (44) 1355-803-000 fax: (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel: (49) 71-31-67-0 fax: (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel: 1(719) 576-3300 fax: 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel: (33) 4-76-58-30-00 fax: (33) 4-76-58-34-80 e-mail literature@atmel.com web site http://www.atmel.com 4202b ? scr ? 07/03 /0m ? atmel corporation 200 3. all rights reserved. atmel and combinations thereof are the registered trademarks of atmel corporation or its subsidiaries. other terms and product names may be the trademarks of others.

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